Patents by Inventor Kerstin C. Schelm
Kerstin C. Schelm has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11175921Abstract: A method is provided. The method is executable by a processor. The method includes receiving, by an instruction issue unit of the processor as an input, a preferred instruction variant from an instruction variant selection logic. The method includes executing, by an execution unit of the processor, the preferred instruction variant. The method includes providing, by the execution unit of the processor, quality feedback to the instruction variant selection logic and evaluating, by the instruction variant selection logic of the processor, the preferred instruction variant based on the quality feedback.Type: GrantFiled: May 15, 2018Date of Patent: November 16, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Juergen Haess, Cedric Lichtenau, Stefan Payer, Kerstin C. Schelm
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Patent number: 10782968Abstract: A substring can be detected within a string of data elements through a method that includes partitioning and distributing the string of data elements to an ordered list of segments having equal lengths greater than or equal to the length of the substring. A substring match within a segment of the ordered list of segments can be detected by sequentially comparing the substring with each segment of the ordered list of segments. A carry vector that includes the substring match can be created, in response to detecting the substring match that is a partial match. It can be determined that a carry vector exists by comparing the substring with the segment of the ordered list of segments, and it can be subsequently determined that a full match exists between the carry vector and the segment of the ordered list of segments.Type: GrantFiled: August 23, 2018Date of Patent: September 22, 2020Assignee: International Business Machines CorporationInventors: Razvan Peter Figuli, Stefan Payer, Cedric Lichtenau, Kerstin C. Schelm
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Publication number: 20200065096Abstract: A substring can be detected within a string of data elements through a method that includes partitioning and distributing the string of data elements to an ordered list of segments having equal lengths greater than or equal to the length of the substring. A substring match within a segment of the ordered list of segments can be detected by sequentially comparing the substring with each segment of the ordered list of segments. A carry vector that includes the substring match can be created, in response to detecting the substring match that is a partial match. It can be determined that a carry vector exists by comparing the substring with the segment of the ordered list of segments, and it can be subsequently determined that a full match exists between the carry vector and the segment of the ordered list of segments.Type: ApplicationFiled: August 23, 2018Publication date: February 27, 2020Inventors: Razvan Peter Figuli, Stefan Payer, Cedric Lichtenau, Kerstin C. Schelm
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Patent number: 10552167Abstract: A system and a method of clock-gating for multicycle instructions are provided. For example, the method includes enabling a plurality of logic blocks that include a subset of multicycle (MC) logic blocks and a subset of pipeline logic blocks. The method also includes computing a precise enable computation value after a plurality of cycles of executing an instruction, and disabling one or more of the subset of multicycle (MC) logic blocks based on the precise enable computation value. Also, at least the subset of pipeline logic blocks needed to compute the instruction remains on.Type: GrantFiled: November 27, 2017Date of Patent: February 4, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Juergen Haess, Cédric Lichtenau, Stefan Payer, Kerstin C. Schelm
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Publication number: 20190354373Abstract: A method is provided. The method is executable by a processor. The method includes receiving, by an instruction issue unit of the processor as an input, a preferred instruction variant from an instruction variant selection logic. The method includes executing, by an execution unit of the processor, the preferred instruction variant. The method includes providing, by the execution unit of the processor, the quality feedback to the instruction variant selection logic. The method includes evaluating, by the instruction variant selection logic of the processor, a quality of the preferred instruction variant correct based on the quality feedback.Type: ApplicationFiled: May 15, 2018Publication date: November 21, 2019Inventors: Juergen Haess, Cedric Lichtenau, Stefan Payer, Kerstin C. Schelm
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Patent number: 10168993Abstract: A logic circuit and a method using thereof for zero detection of a sum of inputs without performing an addition. The logic circuit and the method using thereof perform a true mathematical zero check and a zero check for trailing N-bits. The logic circuit and the method using thereof include bitwise XOR, XNOR, and OR operations, an OR-reduction, an AND reduction, and a control signal that switches between a true mathematical zero check and a zero check for trailing N-bits. The logic circuit and the method using thereof have less timing delay than an adder or a leading zero anticipator for a zero check. The logic circuit and the method using thereof use less logic gates and therefore less area and less power are needed. The logic circuit and the method using thereof have a great advantage for the zero check of large input vectors.Type: GrantFiled: October 20, 2017Date of Patent: January 1, 2019Assignee: International Business Machines CorporationInventors: Michael K. Kroener, Silvia M. Mueller, Manuela Niekisch, Kerstin C. Schelm
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Patent number: 10101967Abstract: A logic circuit and a method using thereof for zero detection of a sum of inputs without performing an addition. The logic circuit and the method using thereof perform a true mathematical zero check and a zero check for trailing N-bits. The logic circuit and the method using thereof include bitwise XOR, XNOR, and OR operations, an OR-reduction, an AND reduction, and a control signal that switches between a true mathematical zero check and a zero check for trailing N-bits. The logic circuit and the method using thereof have less timing delay than an adder or a leading zero anticipator for a zero check. The logic circuit and the method using thereof use less logic gates and therefore less area and less power are needed. The logic circuit and the method using thereof have a great advantage for the zero check of large input vectors.Type: GrantFiled: February 22, 2017Date of Patent: October 16, 2018Assignee: International Business Machines CorporationInventors: Michael K. Kroener, Silvia M. Mueller, Manuela Niekisch, Kerstin C. Schelm
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Publication number: 20180239588Abstract: A logic circuit and a method using thereof for zero detection of a sum of inputs without performing an addition. The logic circuit and the method using thereof perform a true mathematical zero check and a zero check for trailing N-bits. The logic circuit and the method using thereof include bitwise XOR, XNOR, and OR operations, an OR-reduction, an AND reduction, and a control signal that switches between a true mathematical zero check and a zero check for trailing N-bits. The logic circuit and the method using thereof have less timing delay than an adder or a leading zero anticipator for a zero check. The logic circuit and the method using thereof use less logic gates and therefore less area and less power are needed. The logic circuit and the method using thereof have a great advantage for the zero check of large input vectors.Type: ApplicationFiled: February 22, 2017Publication date: August 23, 2018Inventors: Michael K. Kroener, Silvia M. Mueller, Manuela Niekisch, Kerstin C. Schelm
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Publication number: 20180239589Abstract: A logic circuit and a method using thereof for zero detection of a sum of inputs without performing an addition. The logic circuit and the method using thereof perform a true mathematical zero check and a zero check for trailing N-bits. The logic circuit and the method using thereof include bitwise XOR, XNOR, and OR operations, an OR-reduction, an AND reduction, and a control signal that switches between a true mathematical zero check and a zero check for trailing N-bits. The logic circuit and the method using thereof have less timing delay than an adder or a leading zero anticipator for a zero check. The logic circuit and the method using thereof use less logic gates and therefore less area and less power are needed. The logic circuit and the method using thereof have a great advantage for the zero check of large input vectors.Type: ApplicationFiled: October 20, 2017Publication date: August 23, 2018Inventors: Michael K. Kroener, Silvia M. Mueller, Manuela Niekisch, Kerstin C. Schelm
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Patent number: 9977680Abstract: A system and a method of clock-gating for multicycle instructions are provided. For example, the method includes enabling a plurality of logic blocks that include a subset of multicycle (MC) logic blocks and a subset of pipeline logic blocks. The method also includes computing a precise enable computation value after a plurality of cycles of executing an instruction, and disabling one or more of the subset of multicycle (MC) logic blocks based on the precise enable computation value. Also, at least the subset of pipeline logic blocks needed to compute the instruction remains on.Type: GrantFiled: September 30, 2016Date of Patent: May 22, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Juergen Haess, Cédric Lichtenau, Stefan Payer, Kerstin C. Schelm
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Publication number: 20180095768Abstract: A system and a method of clock-gating for multicycle instructions are provided. For example, the method includes enabling a plurality of logic blocks that include a subset of multicycle (MC) logic blocks and a subset of pipeline logic blocks. The method also includes computing a precise enable computation value after a plurality of cycles of executing an instruction, and disabling one or more of the subset of multicycle (MC) logic blocks based on the precise enable computation value. Also, at least the subset of pipeline logic blocks needed to compute the instruction remains on.Type: ApplicationFiled: November 27, 2017Publication date: April 5, 2018Inventors: Juergen Haess, Cédric Lichtenau, Stefan Payer, Kerstin C. Schelm
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Publication number: 20180095767Abstract: A system and a method of clock-gating for multicycle instructions are provided. For example, the method includes enabling a plurality of logic blocks that include a subset of multicycle (MC) logic blocks and a subset of pipeline logic blocks. The method also includes computing a precise enable computation value after a plurality of cycles of executing an instruction, and disabling one or more of the subset of multicycle (MC) logic blocks based on the precise enable computation value. Also, at least the subset of pipeline logic blocks needed to compute the instruction remains on.Type: ApplicationFiled: September 30, 2016Publication date: April 5, 2018Inventors: Juergen Haess, Cédric Lichtenau, Stefan Payer, Kerstin C. Schelm