Abstract: Performing an arithmetic operation in a data processing unit, including calculating a number of iterations for performing the arithmetic operation with a given number of bits per iteration. The number of bits per iteration is a positive natural number. A number of consecutive digit positions of a digit in a sequence of bits represented in the data processing unit is counted. The length of the sequence is a multiple of the number of bits per iteration. A quotient of the number of consecutive digit positions divided by the number of bits per iteration is calculated, as well as a remainder of the division.

Abstract: Logic is provided for performing decimal and binary floating point arithmetic calculations on first and second operands. The method includes: receiving the first and second operands in packed format; unpacking the first and second operands; swapping the first operand to a fourth operand and the second operand to a third operand, if an exponent of the first operand is less than an exponent of the second operand, otherwise storing the first operand to the third operand and the second operand to the fourth operand; aligning the third operand and the fourth operands based on the exponent difference of the third and fourth operand and a number of leading zeroes of the third operand; performing an add/subtract operation on the aligned third and fourth operands with normalizing and rounding between the operands; and packing the result obtained from the add/subtract.

Abstract: Processing within a computing environment is facilitated. An operand of an instruction is obtained, which includes decimal floating point data encoded in a compressed format. An operation is performed on the operand absent decompressing a source value of a trailing significand of the decimal floating point data in the compressed format.

Abstract: An initializable repair circuit and method are provided to facilitate, when enabled, selective replacement of a table-driven output value provided by a lookup structure. The initializable repair circuit includes a compare circuit to identify a cell of the lookup structure based, at least in part, on a first input value and a second input value. The table-driven output value is ascertained, at least in part, using a cell value of the identified cell. The initializable repair circuit further includes a repair enable register and a logic circuit. The repair enable register contains an enable repair indicator to be set when at least one cell value is known to be incorrect, and the logic circuit replaces the incorrect table-driven output value provided by the lookup structure with an initialized replacement value based, at least in part, on the enable repair indicator being set in the repair enable register.

Abstract: Processing within a computing environment is facilitated. An operand of an instruction is obtained, which includes decimal floating point data encoded in a compressed format. An operation is performed on the operand absent decompressing a source value of a trailing significand of the decimal floating point data in the compressed format.

Abstract: An initializable repair circuit and method are provided to facilitate, when enabled, selective replacement of a table-driven output value provided by a lookup structure. The initializable repair circuit includes a compare circuit to identify a cell of the lookup structure based, at least in part, on a first input value and a second input value. The table-driven output value is ascertained, at least in part, using a cell value of the identified cell. The initializable repair circuit further includes a repair enable register and a logic circuit. The repair enable register contains an enable repair indicator to be set when at least one cell value is known to be incorrect, and the logic circuit replaces the incorrect table-driven output value provided by the lookup structure with an initialized replacement value based, at least in part, on the enable repair indicator being set in the repair enable register.

Abstract: An arithmetic operation in a data processing unit, preferably by iterative digit accumulations, is proposed. An approximate result of the arithmetic operation is computed iteratively. Concurrently at least two supplementary values of the approximate result of the arithmetic operation are computed, and the final result selected from one of the values of the approximate result and the at least two supplementary values of the arithmetic operation depending on the results of the last iteration step.

Abstract: An arithmetic operation in a data processing unit, preferably by iterative digit accumulations, is proposed. An approximate result of the arithmetic operation is computed iteratively. Concurrently at least two supplementary values of the approximate result of the arithmetic operation are computed, and the final result selected from one of the values of the approximate result and the at least two supplementary values of the arithmetic operation depending on the results of the last iteration step.

Abstract: Logic is provided for performing decimal and binary floating point arithmetic calculations on first and second operands. The method includes: receiving the first and second operands in packed format; unpacking the first and second operands; swapping the first operand to a fourth operand and the second operand to a third operand, if an exponent of the first operand is less than an exponent of the second operand, otherwise storing the first operand to the third operand and the second operand to the fourth operand; aligning the third operand and the fourth operands based on the exponent difference of the third and fourth operand and a number of leading zeroes of the third operand; performing an add/subtract operation on the aligned third and fourth operands with normalizing and rounding between the operands; and packing the result obtained from the add/subtract.

Abstract: Performing an arithmetic operation in a data processing unit, including calculating a number of iterations for performing the arithmetic operation with a given number of bits per iteration. The number of bits per iteration is a positive natural number. A number of consecutive digit positions of a digit in a sequence of bits represented in the data processing unit is counted. The length of the sequence is a multiple of the number of bits per iteration. A quotient of the number of consecutive digit positions divided by the number of bits per iteration is calculated, as well as a remainder of the division.

Abstract: An arithmetic operation in a data processing unit, preferably by iterative digit accumulations, is proposed. An approximate result of the arithmetic operation is computed iteratively. Concurrently at least two supplementary values of the approximate result of the arithmetic operation are computed, and the final result selected from one of the values of the approximate result and the at least two supplementary values of the arithmetic operation depending on the results of the last iteration step.

Abstract: Mechanisms for utilizing a reduced lookup table circuit to perform an operation in a data processing device are provided. A first input value is input for selecting a subset of values from the reduced lookup table circuit. The reduced lookup table circuit stores only boundary cell values from a fully filled lookup table corresponding to the reduced lookup table circuit. The subset of values comprises only a subset of boundary cell values corresponding to the first input value. A second value is input and a comparison, by the reduced lookup table circuit, of the second value to each of the boundary cell values in the subset of boundary cell values is performed. The reduced lookup table circuit outputs an output value based on results of the comparison of the second value to each of the boundary cell values in the subset of boundary cell values.

Abstract: Mechanisms for utilizing a reduced lookup table circuit to perform an operation in a data processing device are provided. A first input value is input for selecting a subset of values from the reduced lookup table circuit. The reduced lookup table circuit stores only boundary cell values from a fully filled lookup table corresponding to the reduced lookup table circuit. The subset of values comprises only a subset of boundary cell values corresponding to the first input value. A second value is input and a comparison, by the reduced lookup table circuit, of the second value to each of the boundary cell values in the subset of boundary cell values is performed. The reduced lookup table circuit outputs an output value based on results of the comparison of the second value to each of the boundary cell values in the subset of boundary cell values.

Abstract: A technique for checking an exponent calculation for an execution unit that supports floating point operations includes generating, using a residue prediction circuit, a predicted exponent residue for a result exponent of a floating point operation. The technique also includes generating, using an exponent calculation circuit, the result exponent for the floating point operation and generating, using the residue prediction circuit, a result exponent residue for the result exponent. Finally, the technique includes comparing the predicted exponent residue to the result exponent residue to determine whether the result exponent generated by the exponent calculation circuit is correct and, if not, signaling an error.

Abstract: An arithmetic operation in a data processing unit, preferably by iterative digit accumulations, is proposed. An approximate result of the arithmetic operation is computed iteratively. Concurrently at least two supplementary values of the approximate result of the arithmetic operation are computed, and the final result selected from one of the values of the approximate result and the at least two supplementary values of the arithmetic operation depending on the results of the last iteration step.

Abstract: A technique for checking an exponent calculation for an execution unit that supports floating point operations includes generating, using a residue prediction circuit, a predicted exponent residue for a result exponent of a floating point operation. The technique also includes generating, using an exponent calculation circuit, the result exponent for the floating point operation and generating, using the residue prediction circuit, a result exponent residue for the result exponent. Finally, the technique includes comparing the predicted exponent residue to the result exponent residue to determine whether the result exponent generated by the exponent calculation circuit is correct and, if not, signaling an error.

Abstract: Mechanisms for utilizing a reduced lookup table circuit to perform an operation in a data processing device are provided. A first input value is input for selecting a subset of values from the reduced lookup table circuit. The reduced lookup table circuit stores only boundary cell values from a fully filled lookup table corresponding to the reduced lookup table circuit. The subset of values comprises only a subset of boundary cell values corresponding to the first input value. A second value is input and a comparison, by the reduced lookup table circuit, of the second value to each of the boundary cell values in the subset of boundary cell values is performed. The reduced lookup table circuit outputs an output value based on results of the comparison of the second value to each of the boundary cell values in the subset of boundary cell values.

Abstract: Mechanisms for utilizing a reduced lookup table circuit to perform an operation in a data processing device are provided. A first input value is input for selecting a subset of values from the reduced lookup table circuit. The reduced lookup table circuit stores only boundary cell values from a fully filled lookup table corresponding to the reduced lookup table circuit. The subset of values comprises only a subset of boundary cell values corresponding to the first input value. A second value is input and a comparison, by the reduced lookup table circuit, of the second value to each of the boundary cell values in the subset of boundary cell values is performed. The reduced lookup table circuit outputs an output value based on results of the comparison of the second value to each of the boundary cell values in the subset of boundary cell values.

Abstract: A system and a method for storing numbers in a register file are provided. The system and the method store single precision numbers in double precision format in a register file that is shared between floating point computational units and computational units not supporting floating point numbers.

Abstract: In a binary floating point processor, the exponents of each of the various types of operands are recoded into an internal format, by biasing the exponents with the minimum exponent value of the result precision (“Emin”), i.e., the recoded value of the exponent is the represented value of the exponent minus Emin. Emin depends only on the result precision of the instruction that is currently being executed in the binary floating point processor. The exponent computations are then performed in this new format. The underflow check for all result precisions is a check against zero and overflow checks are performed against a positive number that depends on the result precision. The exponent values are in a 2's complement representation, so the underflow check simply becomes a check of the sign bit.