Abstract: A display panel, a display device, and a splicing display device are provided. The display panel includes pixels including subpixels, the subpixel includes a pixel circuit and a light-emitting element that are electrically connected to each other. In a pixel, light-emitting elements of the subpixels are arranged along a first direction, and pixel circuits of the subpixels are arranged along the first direction. In at least one pixel, an arrangement order of the light-emitting elements is different from an arrangement order of the pixel circuits; or arrangement orders of the pixel circuits in at least two pixels are different from each other, or arrangement orders of the light-emitting elements in at least two pixels are different from each other.

Abstract: A driving circuit, a driving method and a microfluidic substrate are provided. The driving circuit includes a first switching unit, a second switching unit, a reset unit, a first capacitor, and a second capacitor. In a first stage of a driving process of the driving circuit, the first switching unit is turned on, a first voltage signal is transmitted to a first node, the second switching unit is turned on, a second voltage signal is input to an output terminal of the driving circuit, and the driving circuit outputs an AC signal. In a second stage of the driving process, the first switching unit is turned off, the valid signal output by the second scan signal terminal controls the reset unit to be turned on, a third voltage signal is input to the output terminal of the driving circuit for reset, and the driving circuit outputs a DC signal.

Abstract: Provided are a driver board, a display panel, and a display apparatus. The driver board includes a driver circuit. The driver circuit includes N pixel electrodes, N pixel switches, a data switch, and a storage capacitor, N is a positive integer, and N?2. The storage capacitor includes a reference electrode and a counter electrode. A control terminal of the pixel switch receives a gating signal, a first terminal of the pixel switch is connected to the counter electrode, and a second terminal of the pixel switch is connected to the pixel electrode. The driver board further includes data lines, and each data line is connected to the counter electrode via the data switch.

Abstract: A gene sequencing structure, a gene sequencing device and a gene sequencing method are provided. The gene sequencing structure includes a substrate, a thin-film transistor array layer located on the substrate and including thin-film transistors that include a first electrode, and a second electrode; an ion-sensitive layer located on a side of the semiconductor layer away from the substrate; a micro-hole layer located on a side of the ion-sensitive layer away from the substrate, including a through-hole passing through the micro-hole layer, at least partially overlapping the semiconductor layer, and used for receiving a to-be-tested single-stranded nucleic acid inside; a conductive structure, located on a side of the layer away from the substrate and electrically connected to the first electrode or the second electrode; and a detection chip, located on a side of the conductive structure away from the substrate and electrically connected to the conductive structure.

Abstract: An antenna includes a first base plate. The first base plate has a phase shifter array area and a bonding area. The first base plate includes a first substrate, a first metal layer, and a first conductive layer. The first conductive layer is made of a high-resistance conductive material. The first metal layer includes conductive pads and phase shifter units. At least some conductive pads are in the bonding area, and at least some phase shifter units are located in the phase shifter array area. The first conductive layer includes bias voltage lines, and one conductive pad is electrically connected to a corresponding phase shifter unit through at least one bias voltage line. At least some sections of one bias voltage line partially overlap with one corresponding phase shifter unit, and at least some sections of one bias voltage line overlap with one corresponding conductive pad.

Abstract: Liquid crystal antenna box, antenna, and method of manufacturing the antenna box are provided. The antenna box includes first baseplate, second baseplate, liquid crystal layer, and insulation layer. The first baseplate includes a first substrate and a first metal layer. The first metal layer includes a ground part and a via between the ground parts. The second baseplate includes a second substrate and a second metal layer. The second metal layer includes a phase shifter and an interval groove between the phase shifters. Surface spacing between the phase shifter, and the insulation layer in the via or a surface of the first substrate close to the second substrate, surface spacing between the ground part, and the insulation layer at the interval groove or a surface of the second substrate close to the first substrate, and surface spacing between the ground part and the phase shifter, are equal.

Abstract: An antenna, a formation method of the antenna, and an antenna group are provided in the present disclosure. The antenna includes a first substrate, a second substrate, a third substrate and a feed source. A first frequency selective surface is on a side of the first substrate; a reflective layer is on a side of the second substrate; a first electrode layer is on a side of the third substrate; and the third substrate is on a side of the second substrate away from the first substrate, and liquid crystal molecules are between the second substrate and the third substrate; or the third substrate is on a side of the first substrate away from the second substrate, and liquid crystal molecules are between the third substrate and the first substrate. The feed source is on the side of the second substrate or on the side of the third substrate.

Abstract: A detection device and a detection method are provided. The detection device includes at least one detection unit. The detection unit includes a first transistor, a second transistor, a third transistor and a fourth transistor that are electrically connected to each other, a gate is disposed above a channel of each of the first transistor, the second transistor, and the third transistor, and an ion-sensitive membrane is covered above a channel of the fourth transistor. The detection device also includes a first voltage signal terminal, a second voltage signal terminal, and a third voltage signal terminal. Further, the detection device includes a first power supply terminal, a first potential output terminal, a second potential output terminal, and a second power supply terminal.

Abstract: A liquid crystal antenna is described. The liquid crystal antenna includes liquid crystal phase shifter units arranged in an array; a first feeding network line corresponding to an ith scanning line and extending along a first direction, and/or, a second feeding network line corresponding to an jth data line and extending along a second direction. The first feeding network line is provided between the ith scanning line and an (i+1)th scanning line, and a scanning line protrusion protrudes toward a side facing away from the first feeding network line corresponding to the ith scanning line. The second feeding network line is provided between the jth data line and a (j+1)th data line, and a data line protrusion protrudes toward a side facing away from the second feeding network line corresponding to the jth data line.

Abstract: Provided circuit structure includes a first voltage division branch and a second voltage division branch. The first voltage division branch includes a first control terminal and a first voltage division output terminal, and the second voltage division branch includes a second control terminal and a second voltage division output terminal. The first control terminal of the first voltage division branch receives a first initial signal V0, and the first voltage division output terminal is electrically connected to the second control terminal of the second voltage division branch. At a first pulse level stage, the second voltage division output terminal outputs a first output level signal, and at a second pulse level stage, the second voltage division output terminal outputs a second output level signal different from the first output level signal.

Abstract: A microfluidic chip and a fabrication method of the microfluidic chip are provided. The microfluidic chip includes an array substrate, and a hydrophobic layer disposed on a side of the array substrate. The hydrophobic layer includes at least one through-hole, and a through-hole of the at least one through-hole penetrates through the hydrophobic layer along a direction perpendicular to a plane of the array substrate. The microfluidic chip also includes at least one hydrophilic structure. A hydrophilic structure of the at least one hydrophilic structure is disposed in the through-hole.

Abstract: Driving circuit, microfluidic driving device and driving method are provided. The driving circuit includes a data writing module, a first inverter and a second inverter. An output terminal of the data writing module is connected to a first node. A first terminal of the first inverter is connected to a first power supply terminal, a second terminal of the first inverter is connected to a second power supply terminal, an input terminal of the first inverter is connected to the first node, and an output terminal of the first inverter is connected to a second node. A first terminal of the second inverter is connected to the first power supply terminal, a second terminal of the second inverter is connected to the second power supply terminal, and an input terminal of the second inverter is connected to the second node.

Abstract: A display panel and a display apparatus are provided. The display panel has a display region. The display panel includes in the display region: a plurality of data lines, a plurality of test switches, a plurality of test signal lines and a plurality of test control lines. One of the plurality of test switches includes an input terminal electrically connected to one of the plurality of test signal lines, an output terminal electrically connected to one of the plurality of data lines, and a control terminal electrically connected to one of the plurality of test control lines.

Abstract: Provided are a phase shifter, a preparation method thereof, and an antenna. The phase shifter includes at least one phase shifting unit, and the phase shifting unit includes a microstrip line, a photo-dielectric layer, a ground electrode, and at least one light guiding structure; the microstrip line is located on a side of the photo-dielectric layer, and the ground electrode is located on a side of the photo-dielectric layer facing away from the microstrip line; the light-guiding structure at least partially overlaps the photo-dielectric layer, and the light-guiding structure is configured to guide light into the photo-dielectric layer.

Abstract: The present disclosure provides chip package structure, packaging method, camera module and electronic equipment. The package structure includes chip package module, which includes light-transmitting substrate, wiring layer located on side of light-transmitting substrate and including first metal wire, conductor located on side of wiring layer facing away from light-transmitting substrate, photosensitive chip located on side of wiring layer facing away from the light-transmitting substrate, active chip located on side of wiring layer facing away from light-transmitting substrate, and plastic encapsulation layer encapsulating photosensitive chip and active chip. The conductor includes first end electrically connected to first metal wire, and second end. The photosensitive chip includes pin electrically connected to first metal wire and has photosensitive surface facing towards light-transmitting substrate. The photosensitive surface includes photosensitive region that is not overlapping first metal wire.

Abstract: A display panel, a splicing screen, and a display apparatus. The display panel comprises an array base plate comprising a substrate as well as a plurality of transistors and a plurality of connection electrodes located on one side of the substrate; the plurality of transistors comprise a first transistor, and the plurality of connection electrodes comprise a first connection electrode; the array base plate has at least one first edge; the first transistor is adjacent to the first edge, and the first connection electrode is adjacent to the first edge, a distance between the first transistor and the first edge is greater than a distance between the first connection electrode and the first edge. The present invention can reduce the risk of failure of the transistors near the cutting edge due to laser cutting in the laser cutting process, and can improve the production yield of narrow-bezel or bezel-free products.

Abstract: Provided are a liquid crystal antenna and a manufacturing method thereof. The liquid crystal antenna includes a first substrate, a second substrate and a third substrate that are stacked. The first substrate and the second substrate constitute a first box-shaped structure. A first space is disposed between the first substrate and the second substrate. The first space is filled with a liquid crystal layer. The second substrate and the third substrate constitute a second box-shaped structure. A second conductive pattern layer is disposed on a side of the second substrate. A third conductive pattern layer is disposed on a single side of the third substrate. A second space is disposed between the second substrate and the third substrate.

Abstract: A substrate module, a display apparatus, and a liquid crystal antenna are provided in the present disclosure. The substrate module includes a first substrate. The first substrate includes a first sub-region and a second sub-region; the second sub-region includes a binding region; and the binding region includes first pins. The first sub-region includes first loads, and a first sub-pin is electrically connected to the first load. The second sub-region includes at least one second load, and a second sub-pin is electrically connected to the second load. The second load includes a capacitor including a first capacitor. The first substrate includes a first base substrate, a first electrode layer, a first insulating layer and a second electrode layer. Along a direction perpendicular to a plane of the base substrate, an overlapping portion of a first electrode portion and a second electrode portion forms the first capacitor.

Abstract: An antenna and a fabrication method of the antenna are provided. The antenna includes a plurality of sub-antennas arranged in an array. A sub-antenna of the plurality of sub-antennas includes a first substrate and a second substrate that are disposed opposite to each other, a dielectric function layer disposed between the first substrate and the second substrate, a ground metal layer disposed on a side of the first substrate facing towards the dielectric function layer, and a metal connector. The first substrate of each sub-antenna is coplanar with each other, and the second substrate of each sub-antenna is coplanar with each other. A spliced region is formed between adjacent two sub-antennas of the plurality of sub-antennas, and in the spliced region, two first substrates of the adjacent two sub-antennas are connected by the metal connector.

Abstract: A semiconductor package includes a semiconductor element, a wiring structure, an encapsulation structure, and a solder ball. The semiconductor element includes a plurality of pins. A side of the wiring structure is electrically connected to the plurality of pins of the semiconductor element. The wiring structure includes at least two first wiring layers. A first insulating layer is disposed between adjacent two first wiring layers of the at least two first wiring layers. The first insulating layer includes a plurality of first through-holes. The adjacent two first wiring layers are electrically connected to each other through the plurality of first through-holes. The encapsulation structure at least partially surrounds the semiconductor element. The solder ball is located on a side of the wiring structure away from the semiconductor element. The solder ball is electrically connected to the at least two first wiring layers.