Patents by Inventor Keshab K. P Parhi

Keshab K. P Parhi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Systolic ring-planarized cylindrical array modular multipler
    Patent number: 7010561
    Abstract: A fast, scalable, systolic modular multiplier based on projection onto planar ring structures is presented. Systolic paradigms of limited fan-out on all signal paths and nearest neighbor interconnections guarantee optimally fast clock rates. Linear throughput scalability with respect to consumed hardware resources is achieved through simultaneous parallel processing of multiple independent data streams. Signal sharing among input and output busses and a common control interface for all independent data streams is made possible, thus benefiting integrated circuit implementations.
    Type: Grant
    Filed: October 9, 2002
    Date of Patent: March 7, 2006
    Inventors: William Lee Freking, Keshab K. P. Parhi
  • Fast parallel cascaded array modular multiplier
    Patent number: 6892215
    Abstract: A fast, parallel modular multiplier is presented which is scalable according to available hardware resources. Linear throughput increases with respect to consumed resources is achieved. Multiple independent data streams may be processed simultaneously, and optimal clock rates are attained by virtue of limited fan-out of all signal paths and nearest neighbor interconnections. Integrated circuit implementation is benefited by the potential for signal sharing among input and output busses and a common control interface for all independent data streams.
    Type: Grant
    Filed: July 10, 2002
    Date of Patent: May 10, 2005
    Inventors: William L. Freking, Keshab K. P Parhi
  • Systolic ring-planarized cylindrical array modular multipler
    Publication number: 20040073587
    Abstract: A fast, scalable, systolic modular multiplier based on projection onto planar ring structures is presented. Systolic paradigms of limited fan-out on all signal paths and nearest neighbor interconnections guarantee optimally fast clock rates. Linear throughput scalability with respect to consumed hardware resources is achieved through simultaneous parallel processing of multiple independent data streams. Signal sharing among input and output busses and a common control interface for all independent data streams is made possible, thus benefiting integrated circuit implementations.
    Type: Application
    Filed: October 9, 2002
    Publication date: April 15, 2004
    Inventors: William Lee Freking, Keshab K. P. Parhi
  • Fast parallel cascaded array modular multiplier
    Publication number: 20040010534
    Abstract: A fast, parallel modular multiplier is presented which is scalable according to available hardware resources. Linear throughput increases with respect to consumed resources is achieved. Multiple independent data streams may be processed simultaneously, and optimal clock rates are attained by virtue of limited fan-out of all signal paths and nearest neighbor interconnections. Integrated circuit implementation is benefited by the potential for signal sharing among input and output busses and a common control interface for all independent data streams.
    Type: Application
    Filed: July 10, 2002
    Publication date: January 15, 2004
    Inventors: William L. Freking, Keshab K.P. Parhi