Patents by Inventor Keshav Bhaktavatson Chintamani

Keshav Bhaktavatson Chintamani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10734978
    Abstract: In described examples, a latch includes circuitry for latching input information. The circuitry can be precharged in response to an indication of a first mode and can latch the input information to an indication of a second mode. The latch can optionally further latch the input information in response to a node for storing the latched input information.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: August 4, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Soman Purushothaman, Sankar Prasad Debnath, Per Torstein Roine, Steven C. Bartling, Keshav Bhaktavatson Chintamani
  • Publication number: 20200212896
    Abstract: In described examples, a latch includes circuitry for latching input information. The circuitry can be precharged in response to an indication of a first mode and can latch the input information to an indication of a second mode. The latch can optionally further latch the input information in response to a node for storing the latched input information.
    Type: Application
    Filed: December 28, 2018
    Publication date: July 2, 2020
    Inventors: Soman Purushothaman, Sankar Prasad Debnath, Per Torstein Roine, Steven C. Bartling, Keshav Bhaktavatson Chintamani
  • Patent number: 10340899
    Abstract: This invention is a retention circuit retaining the state of a circuit node driven by a primary drive circuit. This circuit includes cross coupled first and second inverters and a transmission gate. The transmission gate receives a retention mode signal and isolates the retention circuit and the circuit node when a retention mode is active and connects the retention circuit and the circuit node when the retention mode is inactive. In the preferred embodiment the primary drive circuit is constructed of transistors having a standard voltage threshold and the retention circuit is constructed of transistors having a high voltage threshold greater than said standard voltage threshold. A tristate inverter isolates the retention circuit from the circuit node when not in retention mode and supplies an inverse of a signal from output of said first inverter when in retention mode.
    Type: Grant
    Filed: September 26, 2017
    Date of Patent: July 2, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Soman Purushothaman, Keshav Bhaktavatson Chintamani
  • Publication number: 20180248541
    Abstract: This invention is a retention circuit retaining the state of a circuit node driven by a primary drive circuit. This circuit includes cross coupled first and second inverters and a transmission gate. The transmission gate receives a retention mode signal and isolates the retention circuit and the circuit node when a retention mode is active and connects the retention circuit and the circuit node when the retention mode is inactive. In the preferred embodiment the primary drive circuit is constructed of transistors having a standard voltage threshold and the retention circuit is constructed of transistors having a high voltage threshold greater than said standard voltage threshold. A tristate inverter isolates the retention circuit from the circuit node when not in retention mode and supplies an inverse of a signal from output of said first inverter when in retention mode.
    Type: Application
    Filed: September 26, 2017
    Publication date: August 30, 2018
    Inventors: Soman Purushothaman, Keshav Bhaktavatson Chintamani
  • Patent number: 9496024
    Abstract: A system on a chip (SOC) includes a processor and a memory system coupled to the processor. The memory system includes a static random access memory (SRAM) bank and a memory controller. The SRAM bank includes a first switch coupled to a SRAM array power supply and a source of a transistor of an SRAM storage cell in an SRAM array. The SRAM bank also includes a second switch coupled to a NWELL power supply and a bulk of the transistor of the SRAM storage cell. The second switch is configured to close prior to the first switch closing during power up of the SRAM array.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: November 15, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Srinivasa Raghavan Sridhara, Sanjeev Kumar Suman, Premkumar Seetharaman, Keshav Bhaktavatson Chintamani, Atul Ramakant Lele, Raviprakash S. Rao, Parvinder Kumar Rana, Ajith Subramonia, Vipul K. Singhal, Malav Shrikant Shah, Bharath Kumar Poluri
  • Patent number: 7496154
    Abstract: A hysteresis receiver containing two inverters and a logic controller. The inverters are implemented with threshold voltages equaling Vil and Vih, which together define the hysteresis window. The inverters receive the input signal and generate a respective inverted value. The logic controller propagates as output one of the two inverted values if the two inverted values are equal, and a prior value (corresponding to a previous sample) if the two inverted values are not equal. A receiver circuit with a hysteresis window defined by Vil and Vih, is obtained as a result.
    Type: Grant
    Filed: June 23, 2005
    Date of Patent: February 24, 2009
    Assignee: Texas Instruments Incorporated
    Inventor: Keshav Bhaktavatson Chintamani