Patents by Inventor Ketan Dewan
Ketan Dewan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11881861Abstract: Some examples relate to a system including a pulse modulation (PM) circuit having a PM input and a PM output. The system also includes a load circuit having a load circuit input, and an I/O pad coupling the PM output to the load circuit input. An asymmetry detection circuit has a first asymmetry detection (AD) input coupled to the PM output via a first feedback path, a second AD input coupled to an output node of the I/O pad via a second feedback path, and an AD output coupled to the PM input of the pulse modulation circuit via a control path.Type: GrantFiled: January 26, 2022Date of Patent: January 23, 2024Assignee: Infineon Technologies AGInventors: Sunanda Manjunath, Ketan Dewan, Juergen Schaefer
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Patent number: 11784657Abstract: An analog-to-digital device includes a sampling circuit for sampling an input signal. The sampling circuit stops sampling in response to obtaining a trigger signal. The analog-to-digital device includes an analog-to-digital converter circuit which includes an analog to digital converter (ADC) for converting a sampled input provided from the sampling circuit to digital output.Type: GrantFiled: November 23, 2021Date of Patent: October 10, 2023Assignee: Infineon Technologies AGInventors: Ketan Dewan, Rocco Calabro, Juergen Schaefer, David Schaffenrath
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Publication number: 20230238949Abstract: Some examples relate to a system including a pulse modulation (PM) circuit having a PM input and a PM output. The system also includes a load circuit having a load circuit input, and an I/O pad coupling the PM output to the load circuit input. An asymmetry detection circuit has a first asymmetry detection (AD) input coupled to the PM output via a first feedback path, a second AD input coupled to an output node of the I/O pad via a second feedback path, and an AD output coupled to the PM input of the pulse modulation circuit via a control path.Type: ApplicationFiled: January 26, 2022Publication date: July 27, 2023Inventors: Sunanda Manjunath, Ketan Dewan, Juergen Schaefer
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Patent number: 11705917Abstract: A device is provided for time measurement of a clock-based signal comprising a sample stage comprising a switching device that is driven by a control signal and a capacitance (Cs), wherein the sample stage is arranged to transform an analog input signal in an analog output signal, the device further comprising an analog-to-digital converter to convert the analog output signal into a digital output signal, wherein the input signal applied to the sample stage is a reference signal and wherein the clock-based signal is applied to the control signal. Also, an according method is suggested.Type: GrantFiled: September 7, 2021Date of Patent: July 18, 2023Assignee: Infineon Technologies AGInventors: Mihail Jefremow, Ketan Dewan, Rex Kho, Ralph Mueller-Eschenbach, Juergen Schaefer
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Patent number: 11668763Abstract: An analog fault detection circuit is disclosed. The analog fault detection circuit comprises an input terminal, an input circuit path coupled to the input terminal at a first end and a first sampling switch coupled to the second end of the input circuit path. The first sampling switch is configured to sample an input path voltage at the second end of the input circuit path to provide a first analog to digital converter (ADC) input voltage. The analog fault detection circuit further comprises a first ADC conversion circuit configured to convert the first ADC input voltage to a first digital ADC output; and a first broken wire detection circuit coupled between the first sampling switch and the first ADC conversion circuit, and configured to adaptively pulldown or pullup the first ADC input voltage, in order to detect a fault associated with a first analog circuit path.Type: GrantFiled: May 9, 2022Date of Patent: June 6, 2023Assignee: Infineon Technologies AGInventors: Ketan Dewan, Rocco Calabro, Juergen Schaefer
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Patent number: 11614485Abstract: A safety mechanism device includes measuring whether a first output signal or results meets dynamically adjustable boundary criterion. The safety mechanism compares the first output signal with at least one boundary signal that is dynamically adjusted. The safety mechanism can produce a dynamically or automatically adjusted boundary signal using a second output signal. The second output signal can mimic the first output signal.Type: GrantFiled: May 12, 2021Date of Patent: March 28, 2023Assignee: Infineon Technologies AGInventors: Michael Augustin, Ketan Dewan
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Patent number: 11526389Abstract: A fault check circuit, including a first channel comparator to output a first channel comparator output signal indicating whether a first channel digital signal is outside of a first channel threshold range, wherein the first channel digital signal is A/D converted from a first channel analog signal; a second channel comparator to output a second channel comparator output signal indicating whether a second channel digital signal is outside of a second channel threshold range, wherein the second channel digital signal is A/D converted from a second channel analog signal; and an alarm generator circuit to combine the first and second channel comparator output signals, and output a fault check signal, wherein the first and second channel comparators and the alarm generator circuit are implemented in hardware, and the fault check circuit performs a fault check without software intervention.Type: GrantFiled: June 3, 2020Date of Patent: December 13, 2022Assignee: Infineon Technologies AGInventors: Ketan Dewan, Juergen Schaefer
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Publication number: 20220391524Abstract: An interconnect including an input couplable to a source, and an encoder coupled to the input. The encoder is configured to: group information that is received from the source via a same channel; size the grouped information to a common width; and apply protection to the sized grouped information.Type: ApplicationFiled: June 7, 2021Publication date: December 8, 2022Inventors: Ketan Dewan, Trevor Bird, Simon Cottam, Glenn Ashley Farrall, Darren Galpin, Frank Hellwig, Paul Hubbert, Dietmar Koenig, Shubhendu Mahajan, Sandeep Vangipuram
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Publication number: 20220276323Abstract: An analog fault detection circuit is disclosed. The analog fault detection circuit comprises an input terminal, an input circuit path coupled to the input terminal at a first end and a first sampling switch coupled to the second end of the input circuit path. The first sampling switch is configured to sample an input path voltage at the second end of the input circuit path to provide a first analog to digital converter (ADC) input voltage. The analog fault detection circuit further comprises a first ADC conversion circuit configured to convert the first ADC input voltage to a first digital ADC output; and a first broken wire detection circuit coupled between the first sampling switch and the first ADC conversion circuit, and configured to adaptively pulldown or pullup the first ADC input voltage, in order to detect a fault associated with a first analog circuit path.Type: ApplicationFiled: May 9, 2022Publication date: September 1, 2022Inventors: Ketan Dewan, Rocco Calabro, Juergen Schaefer
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Publication number: 20220179012Abstract: An analog fault detection circuit is disclosed. The analog fault detection circuit comprises an input terminal, an input circuit path coupled to the input terminal at a first end and a first sampling switch coupled to the second end of the input circuit path. The first sampling switch is configured to sample an input path voltage at the second end of the input circuit path to provide a first analog to digital converter (ADC) input voltage. The analog fault detection circuit further comprises a first ADC conversion circuit configured to convert the first ADC input voltage to a first digital ADC output; and a first broken wire detection circuit coupled between the first sampling switch and the first ADC conversion circuit, and configured to adaptively pulldown or pullup the first ADC input voltage, in order to detect a fault associated with a first analog circuit path.Type: ApplicationFiled: December 8, 2020Publication date: June 9, 2022Inventors: Ketan Dewan, Rocco Calabro, Juergen Schaefer
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Patent number: 11353517Abstract: An analog fault detection circuit is disclosed. The analog fault detection circuit comprises an input terminal, an input circuit path coupled to the input terminal at a first end and a first sampling switch coupled to the second end of the input circuit path. The first sampling switch is configured to sample an input path voltage at the second end of the input circuit path to provide a first analog to digital converter (ADC) input voltage. The analog fault detection circuit further comprises a first ADC conversion circuit configured to convert the first ADC input voltage to a first digital ADC output; and a first broken wire detection circuit coupled between the first sampling switch and the first ADC conversion circuit, and configured to adaptively pulldown or pullup the first ADC input voltage, in order to detect a fault associated with a first analog circuit path.Type: GrantFiled: December 8, 2020Date of Patent: June 7, 2022Assignee: Infineon Technologies AGInventors: Ketan Dewan, Rocco Calabro, Juergen Schaefer
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Publication number: 20220166442Abstract: An analog-to-digital device includes a sampling circuit for sampling an input signal. The sampling circuit stops sampling in response to obtaining a trigger signal. The analog-to-digital device includes an analog-to-digital converter circuit which includes an analog to digital converter (ADC) for converting a sampled input provided from the sampling circuit to digital output.Type: ApplicationFiled: November 23, 2021Publication date: May 26, 2022Inventors: Ketan Dewan, Rocco Calabro, Juergen Schaefer, David Schaffenrath
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Publication number: 20220085824Abstract: A device is provided for time measurement of a clock-based signal comprising a sample stage comprising a switching device that is driven by a control signal and a capacitance (Cs), wherein the sample stage is arranged to transform an analog input signal in an analog output signal, the device further comprising an analog-to-digital converter to convert the analog output signal into a digital output signal, wherein the input signal applied to the sample stage is a reference signal and wherein the clock-based signal is applied to the control signal. Also, an according method is suggested.Type: ApplicationFiled: September 7, 2021Publication date: March 17, 2022Inventors: Mihail Jefremow, Ketan Dewan, Rex Kho, Ralph Mueller-Eschenbach, Juergen Schaefer
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Publication number: 20210396806Abstract: A safety mechanism device includes measuring whether a first output signal or results meets dynamically adjustable boundary criterion. The safety mechanism compares the first output signal with at least one boundary signal that is dynamically adjusted. The safety mechanism can produce a dynamically or automatically adjusted boundary signal using a second output signal. The second output signal can mimic the first output signal.Type: ApplicationFiled: May 12, 2021Publication date: December 23, 2021Inventors: Michael Augustin, Ketan Dewan
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Publication number: 20210382776Abstract: A fault check circuit, including a first channel comparator to output a first channel comparator output signal indicating whether a first channel digital signal is outside of a first channel threshold range, wherein the first channel digital signal is A/D converted from a first channel analog signal; a second channel comparator to output a second channel comparator output signal indicating whether a second channel digital signal is outside of a second channel threshold range, wherein the second channel digital signal is A/D converted from a second channel analog signal; and an alarm generator circuit to combine the first and second channel comparator output signals, and output a fault check signal, wherein the first and second channel comparators and the alarm generator circuit are implemented in hardware, and the fault check circuit performs a fault check without software intervention.Type: ApplicationFiled: June 3, 2020Publication date: December 9, 2021Inventors: Ketan Dewan, Juergen Schaefer
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Patent number: 11177987Abstract: Processing a resolver signal by a microcontroller includes generating, by a carrier signal generator, a carrier signal for output to a resolver; receiving modulated carrier signals from a resolver via hardware that is external to the microcontroller; integrating, by an integrator, respective integrator input signals which are based on the modulated carrier signals, to generate respective envelope signals, wherein a start of an integration window of the integrator is set with respect to a start of the carrier signal; and determining an angular position sensed by the resolver based on the envelope signals.Type: GrantFiled: October 27, 2020Date of Patent: November 16, 2021Assignee: Infineon Technologies AGInventors: Mihail Jefremow, Michael Augustin, Ketan Dewan, Ralph Mueller-Eschenbach, Juergen Schaefer
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Patent number: 10816642Abstract: In various embodiments, a circuitry configured to generate a voltage is provided. The circuitry may include a sequence generator configured to provide a sequence of data words consisting of bits. The number of bits is greater than two. The circuitry may further include a delta-sigma modulator configured to receive the sequence of data words provided by the sequence generator and to provide a delta-sigma modulated first single bit data stream at a first data rate, and a decimation filter configured to generate a stream of decimated data words from the first single bit data stream at a second data rate. The second data rate may be smaller than the first data rate, each decimated data word including a plurality of bits. The circuitry may further include a parallel-to-serial converter configured to convert the decimated data words to a second single bit data stream while preserving the second data rate.Type: GrantFiled: June 19, 2018Date of Patent: October 27, 2020Assignee: Infineon Technologies AGInventors: Ketan Dewan, Reinhard Kussian, Juergen Schaefer
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Patent number: 10523190Abstract: A modulator having a pulse density modulator configured to generate from bit stream information a Pulse Density Modulation (PDM) stream based on a PDM clock; and a bit stream adjuster configured to divide the PDM clock into a PDM multi-phase clock, adjust a duration of at least one pulse of the generated PDM stream by selecting a PDM clock phase of the PDM multi-phase clock for sampling the generated PDM stream, and output an adjusted PDM stream.Type: GrantFiled: November 28, 2017Date of Patent: December 31, 2019Assignee: Infineon Technologies AGInventors: Pedro Costa, Ketan Dewan
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Publication number: 20190165775Abstract: A modulator having a pulse density modulator configured to generate from bit stream information a Pulse Density Modulation (PDM) stream based on a PDM clock; and a bit stream adjuster configured to divide the PDM clock into a PDM multi-phase clock, adjust a duration of at least one pulse of the generated PDM stream by selecting a PDM clock phase of the PDM multi-phase clock for sampling the generated PDM stream, and output an adjusted PDM stream.Type: ApplicationFiled: November 28, 2017Publication date: May 30, 2019Inventors: Pedro Costa, Ketan Dewan
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Patent number: 10305506Abstract: A modulator including a delta-sigma modulation circuit having an order greater than 1, and configured to modulate an input signal into a Pulse Density Modulated (PDM) signal; and a Pad Asymmetric Compensation (PAC) circuit configured to linearize a relation between a magnitude of the input signal and a number of rise or fall transitions of the PDM signal by maximizing the number of rise or fall transitions of the PDM signal, and to output a modified PDM signal, wherein the linearized relation is for compensating for any offset in the PDM signal.Type: GrantFiled: August 30, 2017Date of Patent: May 28, 2019Assignee: Infineon Technologies AGInventors: Ketan Dewan, Reinhard Kussian, Juergen Schaefer