Abstract: An integrated circuit includes a first vertical clock bus and a first interface circuit coupled to provide first global clock signals to the first vertical clock bus. The first interface circuit is coupled to a first external terminal of the integrated circuit. The integrated circuit also includes a second vertical clock bus and a second interface circuit coupled to provide second global clock signals to the second vertical clock bus. The second interface circuit is coupled to a second external terminal of the integrated circuit. A third horizontal clock bus is coupled to provide the first and the second global clock signals from the first and the second vertical clock buses to a center region of the integrated circuit.

Abstract: A programmable logic device (PLD) includes at least two regions. Each region includes electrical circuitry that has a set of transistors. Each of the two regions has a corresponding fixed transistor threshold voltage, a corresponding fixed transistor body bias, and a corresponding fixed supply voltage.

Abstract: A programmable logic device (PLD) includes at least two regions. Each region includes electrical circuitry that has a set of transistors. Each of the two regions has a corresponding fixed transistor threshold voltage, a corresponding fixed transistor body bias, and a corresponding fixed supply voltage.

Abstract: A programmable logic device (PLD) includes at least two regions. Each region includes electrical circuitry that has a set of transistors. Each of the two regions has a corresponding fixed transistor threshold voltage, a corresponding fixed transistor body bias, and a corresponding fixed supply voltage.

Abstract: A programmable logic device having logic block that can be selectively placed in a reduced power consumption mode is provided. The PLD includes a plurality of logic array blocks (LABs) and a plurality of interconnects defining signal pathways between the plurality of LABs. Sleep control logic of the PLD issues a sleep control signal for placing at least a portion of the plurality of LABs in a sleep mode. Bias control logic of the PLD is in communication with the sleep control logic. The bias control logic is triggered by the sleep control signal to issue a first bias control signal and a second bias control signal. The first and second bias control signals are transmitted to corresponding transistors of the LABS. The first and second bias control signals apply a reverse bias to corresponding transistor wells to increase threshold voltages for the respective transistors.

Abstract: A programmable logic device has a plurality of super-regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of super-regions. Horizontal and vertical inter-super-region interconnection conductors are associated with each row and column, respectively. Each super-region includes a plurality of regions of programmable logic, and each region includes a plurality of subregions of programmable logic. Inter-region interconnection conductors are associated with each super-region, principally for bringing signals into the super-region and interconnecting the regions in the super-region. Local conductors are associated with each region, principally for bringing signals into the region. At the super-region level the device may be horizontally and vertically isomorphic, which helps make it possible to produce devices with low aspect ratios of one or nearly one. Shared driver circuits may be provided (e.g.

Abstract: A programmable logic device has a plurality of super-regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of super-regions. Horizontal and vertical inter-super-region interconnection conductors are associated with each row and column, respectively. Each super-region includes a plurality of regions of programmable logic, and each region includes a plurality of sub-regions of programmable logic. Inter-region interconnection conductors are associated with each super-region, principally for bringing signals into the super-region and interconnecting the regions in the super-region. Local conductors are associated with each region, principally for bringing signals into the region. At the super-region level the device may be horizontally and vertically isomorphic, which helps make it possible to produce devices with low aspect ratios of one or nearly one. Shared driver circuits may be provided (e.g.

Abstract: A programmable logic device has a plurality of super-regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of super-regions. Horizontal and vertical inter-super-region interconnection conductors are associated with each row and column, respectively. Each super-region includes a plurality of regions of programmable logic, and each region includes a plurality of subregions of programmable logic. Inter-region interconnection conductors are associated with each super-region. Local conductors are associated with each region. Shared driver circuits may be provided (e.g., for (1) receiving signals from the subregions and the horizontal and/or vertical conductors, and (2) applying selected received signals to the inter-region conductors, the horizontal and vertical conductors, and possibly also the local conductors).

Abstract: A programmable logic device has a plurality of super-regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of super-regions. Horizontal and vertical inter-super-region interconnection conductors are associated with each row and column, respectively. Each super-region includes a plurality of regions of programmable logic, and each region includes a plurality of subregions of programmable logic. Inter-region interconnection conductors are associated with each super-region, principally for bringing signals into the super-region and interconnecting the regions in the super-region. Local conductors are associated with each region, principally for bringing signals into the region. At the super-region level the device may be horizontally and vertically isomorphic, which helps make it possible to produce devices with low aspect ratios of one or nearly one. Shared driver circuits may be provided (e.g.

Abstract: A programmable logic device is provided in which logic array blocks (LABs) may be programmably configured for use as one of a variety of memory structures. The configurable memory structures may have separate read and write addresses, thereby making it possible to implement a variety of memory structures such as FIFO memory, ROM, RAM, and shift-registers.

Abstract: A programmable logic device has a plurality of super-regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of super-regions. Horizontal and vertical inter-super-region interconnection conductors are associated with each row and column, respectively. Each super-region includes a plurality of regions of programmable logic, and each region includes a plurality of subregions of programmable logic. Inter-region interconnection conductors are associated with each super-region, principally for bringing signals into the super-region and interconnecting the regions in the super-region. Local conductors are associated with each region, principally for bringing signals into the region. At the super-region level the device may be horizontally and vertically isomorphic, which helps make it possible to produce devices with low aspect ratios of one or nearly one. Shared driver circuits may be provided (e.g.

Abstract: A programmable logic device has a plurality of super-regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of super-regions. Horizontal and vertical inter-super-region interconnection conductors are associated with each row and column, respectively. Each super-region includes a plurality of regions of programmable logic, and each region includes a plurality of subregions of programmable logic. Inter-region interconnection conductors are associated with each super-region, principally for bringing signals into the super-region and interconnecting the regions in the super-region. Local conductors are associated with each region, principally for bringing signals into the region. At the super-region level the device may be horizontally and vertically isomorphic, which helps make it possible to produce devices with low aspect ratios of one or nearly one. Shared driver circuits may be provided (e.g.

Abstract: A logic array block (LAB) that is programmably selectively configurable for use as a multifunction memory array is provided. The LAB is configurable for operation in at least two modes: in a first mode, each logic element within the LAB is individually configurable to perform logic functions; in a second mode, the logic elements are collectively usable as a multifunction memory array. The multifunction memory array may be addressed on a LAB-wide basis with separate read and write addresses, such that it may be configured to implement a variety of memory schemes, including first-in-first-out (FIFO) memory and random access memory (RAM).

Abstract: In order to facilitate the performance of multiplications in programmable logic devices, individual logic modules of such devices are constructed so that one logic module can perform (at least) both one place of binary multiplication and one place of full binary addition. This makes it possible to reduce the number of logic modules that are required to perform a multiplication. It also reduces the number of inter-module connections employed in a multiplication, thereby tending to decrease the time required to perform a multiplication.

Abstract: A programmable logic device has a plurality of super-regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of super-regions. Horizontal and vertical inter-super-region interconnection conductors are associated with each row and column, respectively. Each super-region includes a plurality of regions of programmable logic, and each region includes a plurality of subregions of programmable logic. Inter-region interconnection conductors are associated with each super-region, principally for bringing signals into the super-region and interconnecting the regions in the super-region. Local conductors are associated with each region, principally for bringing signals into the region. At the super-region level the device may be horizontally and vertically isomorphic, which helps make it possible to produce devices with low aspect ratios of one or nearly one. Shared driver circuits may be provided (e.g.

Abstract: In order to facilitate the performance of multiplications in programmable logic devices, individual logic modules of such devices are constructed so that one logic module can perform (at least) both one place of binary multiplication and one place of full binary addition. This makes it possible to reduce the number of logic modules that are required to perform a multiplication. It also reduces the number of inter-module connections employed in a multiplication, thereby tending to decrease the time required to perform a multiplication.

Abstract: A programmable logic device has a plurality of super-regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of super-regions. Horizontal and vertical inter-super-region interconnection conductors are associated with each row and column, respectively. Each super-region includes a plurality of regions of programmable logic, and each region includes a plurality of subregions of programmable logic. Inter-region interconnection conductors are associated with each super-region, principally for bringing signals into the super-region and interconnecting the regions in the super-region. Local conductors are associated with each region, principally for bringing signals into the region. At the super-region level the device may be horizontally and vertically isomorphic, which helps make it possible to produce devices with low aspect ratios of one or nearly one. Shared driver circuits may be provided (e.g.