Patents by Inventor Ketan P. Joshi

Ketan P. Joshi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Split write data processing mechanism for memory controllers utilizing inactive periods during write data processing for other transactions
    Patent number: 6880057
    Abstract: A memory controller provides fast processing of sequential split memory access instructions which include a split write instruction. In a split write instruction, a write address and write request are provided to the memory controller in an initial transaction while write data can be provided to the memory controller in a later transaction. The memory controller includes a sideline buffer, for buffering incomplete write instructions, and memory control logic which ensures proper execution of the sequential memory access instructions. Upon receiving an incomplete write instruction, the memory control logic stores the corresponding write request and write address in the sideline buffer until corresponding write data becomes available. The memory control logic determines if there is overlap between memory space to be occupied by an initial write data block and memory space to be occupied by a subsequent read data block or second write data block, of a read or write instruction respectively.
    Type: Grant
    Filed: January 5, 2000
    Date of Patent: April 12, 2005
    Assignee: Sun Microsystems, Inc.
    Inventors: Thomas P. Webber, Ketan P. Joshi
  • Split write data processing mechanism for memory controllers utilizing inactive periods during write data processing for other transactions
    Patent number: 6061772
    Abstract: A memory controller provides fast processing of sequential split memory access instructions which include a split write instruction. In a split write instruction, a write address and write request are provided to the memory controller in an initial transaction while write data can be provided to the memory controller in a later transaction. The memory controller includes a sideline buffer, for buffering incomplete write instructions, and memory control logic which ensures proper execution of the sequential memory access instructions. Upon receiving an incomplete write instruction, the memory control logic stores the corresponding write request and write address in the sideline buffer until corresponding write data becomes available. The memory control logic determines if there is overlap between memory space to be occupied by an initial write data block and memory space to be occupied by a subsequent read data block or second write data block, of a read or write instruction respectively.
    Type: Grant
    Filed: June 30, 1997
    Date of Patent: May 9, 2000
    Assignee: Sun Microsystems, Inc.
    Inventors: Thomas P. Webber, Ketan P. Joshi