Abstract: A computer system maintaining cache coherency among a plurality of caching devices coupled across a local bus includes a bus master, a memory, and a plurality of cache complexes, all coupled to the local bus. When the bus master requests a read or write with the memory, the cache complexes snoop the transaction. Each cache complex asserts a busy signal during the snooping process. A detection circuit detects when the busy signals have been de-asserted and asserts a done signal. If one of the snoops results in a cache hit to a dirty line, the respective cache complex asserts a dirty signal. If one of the snoops results in a cache hit to a clean line, the respective cache complex asserts a clean signal. If the memory detects a simultaneous assertion of the dirty signal and the done signal, it halts the transaction request from the bus master.