Patents by Inventor Ketan Sodha
Ketan Sodha has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8410579Abstract: In one embodiment, an integrated circuit (IC) is presented. The IC includes first and second sets of power distribution lines formed in the IC. The IC includes first and second capacitors formed in one or more layers of the IC. A first plurality of vias couple a first input of the first and second capacitors to the first set of power distribution lines, and a second plurality of vias couple a second input of the first and second capacitors to the second set of power distribution lines. The first capacitor and the first plurality of vias and the second plurality of vias coupled thereto having an equivalent series resistance greater than an equivalent series resistance of the second capacitor and the first plurality of vias and the second plurality of vias coupled thereto.Type: GrantFiled: December 7, 2010Date of Patent: April 2, 2013Assignee: Xilinx, Inc.Inventors: Atul V. Ghia, Christopher P. Wyland, Ketan Sodha, Paul T. Sasaki, Jian Tan, Paul Y. Wu, Romi Mayder
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Method and apparatus for a process, voltage, and temperature variation tolerant semiconductor device
Patent number: 8222954Abstract: A method and apparatus to reduce the degradation in performance of semiconductor-based devices due to process, voltage, and temperature (PVT) and/or other causes of variation. Adaptive feedback mechanisms are employed to sense and correct performance degradation, while simultaneously facilitating configurability within integrated circuits (ICs) such as programmable logic devices (PLDs). A voltage-feedback mechanism is employed to detect PVT variation and mirrored current references are adaptively adjusted to track and substantially eliminate the PVT variation. More than one voltage-feedback mechanism may instead be utilized to detect PVT-based variations within a differential device, whereby a first voltage-feedback mechanism is utilized to detect common-mode voltage variation and a second voltage-feedback mechanism produces mirrored reference currents to substantially remove the common-mode voltage variation and facilitate symmetrical operation of the differential device.Type: GrantFiled: January 29, 2009Date of Patent: July 17, 2012Assignee: Xilinx, Inc.Inventors: Guo Jun Ren, Qi Zhang, Ketan Sodha -
Publication number: 20120139083Abstract: In one embodiment, an integrated circuit (IC) is presented. The IC includes first and second sets of power distribution lines formed in the IC. The IC includes first and second capacitors formed in one or more layers of the IC. A first plurality of vias couple a first input of the first and second capacitors to the first set of power distribution lines, and a second plurality of vias couple a second input of the first and second capacitors to the second set of power distribution lines. The first capacitor and the first plurality of vias and the second plurality of vias coupled thereto having an equivalent series resistance greater than an equivalent series resistance of the second capacitor and the first plurality of vias and the second plurality of vias coupled thereto.Type: ApplicationFiled: December 7, 2010Publication date: June 7, 2012Applicant: Xilinx, Inc.Inventors: Atul V. Ghia, Christopher P. Wyland, Ketan Sodha, Paul T. Sasaki, Jian Tan, Paul Y. Wu, Romi Mayder
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Patent number: 8018250Abstract: An embodiment of a method for operation of an input/output block is disclosed. For this embodiment of the method, a first attribute is set for a first disable signal for an input driver. A first tri-state condition is removed from an output driver. In response to the removing of the first tri-state condition, the input driver is placed in a second tri-state condition.Type: GrantFiled: October 19, 2010Date of Patent: September 13, 2011Assignee: Xilinx, Inc.Inventors: Matthew H. Klein, Jian Tan, Ketan Sodha, Madan M. Patra
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Method and apparatus for a process, voltage, and temperature variation tolerant semiconductor device
Patent number: 7728630Abstract: A method and apparatus to reduce the degradation in performance of semiconductor-based devices due to process, voltage, and temperature (PVT) and/or other causes of variation. Adaptive feedback mechanisms are employed to sense and correct performance degradation, while simultaneously facilitating configurability within integrated circuits (ICs) such as programmable logic devices (PLDs). A voltage-feedback mechanism is employed to detect PVT variation and mirrored current references are adaptively adjusted to track and substantially eliminate the PVT variation. More than one voltage-feedback mechanism may instead be utilized to detect PVT-based variations within a differential device, whereby a first voltage-feedback mechanism is utilized to detect common-mode voltage variation and a second voltage-feedback mechanism produces mirrored reference currents to substantially remove the common-mode voltage variation and facilitate symmetrical operation of the differential device.Type: GrantFiled: January 29, 2009Date of Patent: June 1, 2010Assignee: XILINX, INC.Inventors: Guo Jun Ren, Qi Zhang, Ketan Sodha -
Patent number: 7317773Abstract: Method and apparatus for doubling the throughput rate of data transmission on a logic path comprising providing two latches that alternately receive successive bits of the data stream to be transmitted and a multiplexer having data transmission paths that are alternately clocked by two separate clocks, which clocks are substantially 180 degrees out of phase.Type: GrantFiled: July 9, 2004Date of Patent: January 8, 2008Assignee: Xilinx, Inc.Inventors: Steven P. Young, Suresh M. Menon, Ketan Sodha, Richard A. Carberry, Joseph H. Hassoun
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Patent number: 7091890Abstract: A serializer-deserializer instantiated in configurable logic of an integrated circuit is described. The serializer-deserializer includes an input deserializer and an output serializer, which may be commonly coupled via an input/output pad. Each of the serializer and deserializer may be configured for an operating mode selected from a Single Data Rate mode and a Double Data Rate mode. The serializer-deserializer may be used as part of a synchronous interface.Type: GrantFiled: August 17, 2004Date of Patent: August 15, 2006Assignee: Xilinx, Inc.Inventors: Paul T. Sasaki, Jason R. Bergendahl, Atul Ghia, Hassan Bazargan, Ketan Sodha, Jian Tan, Qi Zhang, Suresh Menon
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Patent number: 6963219Abstract: A configurable low voltage differential signal (LVDS) system is located on a chip, such as a programmable logic device. The configurable LVDS system includes a pair of I/O pads, an LVDS transmitter for driving a differential output signal onto the I/O pads, an LVDS receiver for receiving a differential input signal from the I/O pads, and a termination resistor coupled across the pair of I/O pads, wherein the termination resistance can be enabled for use with either the LVDS transmitter or the LVDS receiver. Control circuitry is provided to control the selective enabling and disabling of the LVDS transmitter, the LVDS receiver and the termination resistance. This control circuitry can be configured in response to configuration data values stored on the chip.Type: GrantFiled: April 8, 2003Date of Patent: November 8, 2005Assignee: Xilinx, Inc.Inventors: Atul V. Ghia, Ketan Sodha
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Publication number: 20040239365Abstract: Method and apparatus for doubling the throughput rate of data transmission on a logic path comprising providing two latches that alternately receive successive bits of the data stream to be transmitted and a multiplexer having data transmission paths that are alternately clocked by two separate clocks, which clocks are substantially 180 degrees out of phase.Type: ApplicationFiled: July 9, 2004Publication date: December 2, 2004Applicant: Xilinx, Inc.Inventors: Steven P. Young, Suresh M. Menon, Ketan Sodha, Richard A. Carberry, Joseph H. Hassoun
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Patent number: 6777980Abstract: Method and apparatus for doubling the throughput rate of data transmission on a logic path comprising providing two latches that alternately receive successive bits of the data stream to be transmitted and a multiplexer having data transmission paths that are alternately clocked by two separate clocks, which clocks are substantially 180 degrees out of phase.Type: GrantFiled: January 15, 2003Date of Patent: August 17, 2004Assignee: Xilinx, Inc.Inventors: Steven P. Young, Suresh M. Menon, Ketan Sodha, Richard A. Carberry, Joseph H. Hassoun
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Publication number: 20030112032Abstract: Method and apparatus for doubling the throughput rate of data transmission on a logic path comprising providing two latches that alternately receive successive bits of the data stream to be transmitted and a multiplexer having data transmission paths that are alternately clocked by two separate clocks, which clocks are substantially 180 degrees out of phase.Type: ApplicationFiled: January 15, 2003Publication date: June 19, 2003Applicant: Xilinx, Inc.Inventors: Steven P. Young, Suresh M. Menon, Ketan Sodha, Richard A. Carberry, Joseph H. Hassoun
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Patent number: 6531892Abstract: Described are systems for producing differential logic signals and circuits for biasing the voltages of the differential logic signals. These systems can be adapted for use with different loads by programming one or more programmable elements. One embodiment includes a series of driver stages, the outputs of which are connected to one another. The driver stages turn on successively to provide increasingly powerful differential amplification. This progressive increase in amplification produces a corresponding progressive decrease in output resistance, which reduces the noise associated with signal reflection. The systems can be incorporated into programmable IOBs to enable PLDs to provide differential output signals.Type: GrantFiled: January 14, 2002Date of Patent: March 11, 2003Assignee: Xilinx Inc.Inventors: Atul V. Ghia, Ketan Sodha
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Patent number: 6525565Abstract: Method and apparatus for doubling the throughput rate of data transmission on a logic path comprising providing two latches that alternately receive successive bits of the data stream to be transmitted and a multiplexer having data transmission paths that are alternately clocked by two separate clocks, which clocks are substantially 180 degrees out of phase.Type: GrantFiled: January 12, 2001Date of Patent: February 25, 2003Assignee: Xilinx, Inc.Inventors: Steven P. Young, Suresh M. Menon, Ketan Sodha, Richard A. Carberry, Joseph H. Hassoun
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Publication number: 20020175704Abstract: Method and apparatus for doubling the throughput rate of data transmission on a logic path comprising providing two latches that alternately receive successive bits of the data stream to be transmitted and a multiplexer having data transmission paths that are alternately clocked by two separate clocks, which clocks are substantially 180 degrees out of phase.Type: ApplicationFiled: January 12, 2001Publication date: November 28, 2002Inventors: Steven P. Young, Suresh M. Menon, Ketan Sodha, Richard A. Carberry, Joseph H. Hassoun
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Publication number: 20020060602Abstract: Described are systems for producing differential logic signals and circuits for biasing the voltages of the differential logic signals. These systems can be adapted for use with different loads by programming one or more programmable elements. One embodiment includes a series of driver stages, the outputs of which are connected to one another. The driver stages turn on successively to provide increasingly powerful differential amplification. This progressive increase in amplification produces a corresponding progressive decrease in output resistance, which reduces the noise associated with signal reflection. The systems can be incorporated into programmable IOBs to enable PLDs to provide differential output signals.Type: ApplicationFiled: January 14, 2002Publication date: May 23, 2002Applicant: Xilinx, Inc.Inventors: Atul V. Ghia, Ketan Sodha