Abstract: The content and order of a predetermined sequence of hard-coded and/or quasi-programmable test patterns may be altered during a Built-In Self-Test (BIST) routine. As such, knowledge gained post design completion may be reflected in the selection and arrangement of available tests to be executed during a BIST routine. In one embodiment, a sequence of hard-coded and/or quasi-programmable tests is executed during a BIST routine by receiving test ordering information for the sequence of tests and executing the sequence of tests in an order indicated by the test ordering information. A corresponding BIST circuit comprises a storage element and a state machine. The storage element is configured to store test ordering information for the sequence of tests. The state machine is configured to execute the sequence of tests in an order indicated by the test ordering information.

Abstract: The content and order of a predetermined sequence of hard-coded and/or quasi-programmable test patterns may be altered during a Built-In Self-Test (BIST) routine. As such, knowledge gained post design completion may be reflected in the selection and arrangement of available tests to be executed during a BIST routine. In one embodiment, a sequence of hard-coded and/or quasi-programmable tests is executed during a BIST routine by receiving test ordering information for the sequence of tests and executing the sequence of tests in an order indicated by the test ordering information. A corresponding BIST circuit comprises a storage element and a state machine. The storage element is configured to store test ordering information for the sequence of tests. The state machine is configured to execute the sequence of tests in an order indicated by the test ordering information.

Abstract: A method and system for manufacturing integrated circuit devices having multiple memory units embedded therein. Initially, a single reusable configurable test circuit is fabricated within an integrated circuit device. A number and type of each memory unit embedded within the integrated circuit device are then identified. Finally, the single reusable configurable test circuit is configured, in response to the identifying of a number and type of each memory unit, such that only one test circuit is required for use with multiple integrated circuit devices having multiple diverse memory units embedded therein. The single reusable configurable test circuit can be placed within or outside a fixed core of the integrated circuit device. In addition, the single reusable configurable test circuit can include array built-in self test (ABIST) controller which includes a hierarchical memory configuration that includes a state machine, address counter, compare register and data pattern generator.