Patents by Inventor Ketankumar H. Tailor

Ketankumar H. Tailor has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12113070
    Abstract: Structures including a vertical heterojunction bipolar transistor and methods of forming a structure including a vertical heterojunction bipolar transistor. The structure comprises a semiconductor substrate including a trench, a first semiconductor layer including a portion adjacent to the trench, a dielectric layer between the first semiconductor layer and the semiconductor substrate, and a second semiconductor layer in the trench. The dielectric layer has an interface with the first semiconductor layer, and the second semiconductor layer includes a portion that is recessed relative to the interface. The structure further comprises a vertical heterojunction bipolar transistor including a collector in the portion of the second semiconductor layer.
    Type: Grant
    Filed: June 2, 2022
    Date of Patent: October 8, 2024
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Peter Baars, Viorel Ontalus, Ketankumar H. Tailor, Michael Zier, Crystal R. Kenney, Judson Holt
  • Publication number: 20230395607
    Abstract: Structures including a vertical heterojunction bipolar transistor and methods of forming a structure including a vertical heterojunction bipolar transistor. The structure comprises a semiconductor substrate including a trench, a first semiconductor layer including a portion adjacent to the trench, a dielectric layer between the first semiconductor layer and the semiconductor substrate, and a second semiconductor layer in the trench. The dielectric layer has an interface with the first semiconductor layer, and the second semiconductor layer includes a portion that is recessed relative to the interface. The structure further comprises a vertical heterojunction bipolar transistor including a collector in the portion of the second semiconductor layer.
    Type: Application
    Filed: June 2, 2022
    Publication date: December 7, 2023
    Inventors: Peter Baars, Viorel Ontalus, Ketankumar H. Tailor, Michael Zier, Crystal R. Kenney, Judson Holt
  • Patent number: 11456364
    Abstract: Embodiments of the disclosure provide an integrated circuit device and related methods. The disclosure may provide a transistor device, including: a gate structure; a drain extension region extending laterally from partially under the gate structure to a drain region; and a gate spacer located over the drain extension region. A silicide-blocking layer is over and in contact with the gate spacer. The silicide-blocking layer has a first end over the gate structure and a second, opposing end over the drain extension region. The structure also provides a conductive field plate, including a conductive layer over and in contact with the silicide-blocking layer. A field plate contact is formed on the conductive field plate.
    Type: Grant
    Filed: September 23, 2020
    Date of Patent: September 27, 2022
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Ketankumar H. Tailor, Peter Baars, Ruchil K. Jain
  • Publication number: 20220093751
    Abstract: Embodiments of the disclosure provide an integrated circuit device and related methods. The disclosure may provide a transistor device, including: a gate structure; a drain extension region extending laterally from partially under the gate structure to a drain region; and a gate spacer located over the drain extension region. A silicide-blocking layer is over and in contact with the gate spacer. The silicide-blocking layer has a first end over the gate structure and a second, opposing end over the drain extension region. The structure also provides a conductive field plate, including a conductive layer over and in contact with the silicide-blocking layer. A field plate contact is formed on the conductive field plate.
    Type: Application
    Filed: September 23, 2020
    Publication date: March 24, 2022
    Inventors: Ketankumar H. Tailor, Peter Baars, Ruchil K. Jain