Patents by Inventor Keum-seok Park

Keum-seok Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190379241
    Abstract: A power transmitting unit is provided. The power transmitting unit includes a signal generator configured to generate a signal of a first frequency band for wireless charging, a power generation circuit configured to generate a modulation signal for modulating the signal of the first frequency band generated by the signal generator, and amplify a transmit power of the signal of the first frequency band based on voltage supplied from the outside of the power transmitting unit, a power transmission circuit configured to transmit the amplified transmit power to a power receiving unit via a first antenna, a second antenna configured to receive information about a charging state from the power receiving unit through a second frequency band, and a control circuit configured to control a duty and frequency of the modulation signal based on the charging state.
    Type: Application
    Filed: August 22, 2017
    Publication date: December 12, 2019
    Inventors: Dong Zo KIM, Kyoung Won KIM, Han Seok PARK, Se Ho PARK, Yu Su KIM, Keum Su SONG, Ju Hyang LEE, Hyung Koo CHUNG, Kyung Min PARK, Yong Sang YUN
  • Publication number: 20190326768
    Abstract: An apparatus for changing a wireless charging mode includes a power receiving antenna configured to receive power from a power supply using a first frequency band, a communication circuit configured to communicate with the power supply using a second frequency band, a power management circuit configured to charge a battery using the received power, and a control circuit configured to be electrically connected with the power management circuit. In addition, various embodiments ascertained through the specification are possible.
    Type: Application
    Filed: July 5, 2017
    Publication date: October 24, 2019
    Inventors: Han Seok PARK, Young Mi HA, Kang Ho BYUN, Min Ho KANG, Dong Zo KIM, Se Ho PARK, Keum Su SONG
  • Publication number: 20190309415
    Abstract: A method of manufacturing a semiconductor device includes disposing a gas-storage cylinder storing monochlorosilane within a gas supply unit. The monochlorosilane is supplied from the gas-storage cylinder into a process chamber to form a silicon containing layer therein. The gas-storage cylinder includes manganese.
    Type: Application
    Filed: November 26, 2018
    Publication date: October 10, 2019
    Applicant: SK-MATERIALS CO., LTD.
    Inventors: Yeonock Han, Wonwoong Chung, Keum Seok Park, Pankwi Park, Jeongho Yoo, Younjoung Cho, Byung Koo Kong, Mijeong Kim, Jin Wook Lee, Changeun Jang
  • Patent number: 10359301
    Abstract: The present invention relates to a signal processing device for monitoring states of wind-power turbine blades and a method thereof, the signal processing device comprising: an optical fiber sensor unit for sensing moment of rotation of three blades so as to output the moment of rotation as blade signals; a signal transformation unit for converting three blade signals into two fore-ape signals; a rotation information input unit for sensing rotation information of the blades; a rotation speed estimation unit for estimating a rotation speed of the blades on the basis of the rotation information; a state determination unit which removes rotation components from the fore-ape signals and determines whether an operation of a blade is abnormal; and an output unit for outputting the determination result.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: July 23, 2019
    Assignee: Korea Electric Power Corporation
    Inventors: Jae Kyung Lee, Joon Young Park, Jun Shin Lee, Byung Mok Park, Keum Seok Kang, Moo Sung Ryu, Ji Young Kim, Seok Tae Kim, Dae Soo Lee
  • Publication number: 20190214498
    Abstract: A semiconductor device has a silicide source/drain region is fabricated by growing silicon on an epitaxial region including silicon and either germanium or carbon. In the method, a gate electrode is formed on a semiconductor substrate with a gate insulating layer interposed therebetween. An epitaxial layer is formed in the semiconductor substrate at both sides of the gate electrodes. A silicon layer is formed to cap the epitaxial layer. The silicon layer and a metal material are reacted to form a silicide layer. In a PMOS, the epitaxial layer has a top surface and inclined side surfaces that are exposed above the upper surface of the active region. The silicon layer is grown on the epitaxial layer in such a way as to cap the top and inclined surfaces.
    Type: Application
    Filed: March 12, 2019
    Publication date: July 11, 2019
    Inventors: Sungkwan Kang, Keum Seok Park, Byeongchan Lee, Sangbom Kang, Nam-Kyu Kim
  • Patent number: 10263109
    Abstract: A semiconductor device has a silicide source/drain region is fabricated by growing silicon on an epitaxial region including silicon and either germanium or carbon. In the method, a gate electrode is formed on a semiconductor substrate with a gate insulating layer interposed therebetween. An epitaxial layer is formed in the semiconductor substrate at both sides of the gate electrodes. A silicon layer is formed to cap the epitaxial layer. The silicon layer and a metal material are reacted to form a silicide layer. In a PMOS, the epitaxial layer has a top surface and inclined side surfaces that are exposed above the upper surface of the active region. The silicon layer is grown on the epitaxial layer in such a way as to cap the top and inclined surfaces.
    Type: Grant
    Filed: January 14, 2016
    Date of Patent: April 16, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sungkwan Kang, Keum Seok Park, Byeongchan Lee, Sangbom Kang, Nam-Kyu Kim
  • Patent number: 10208401
    Abstract: Disclosed is a substrate treating apparatus comprising a wafer chuck on which a substrate is placed, an injector unit on a side of the wafer chuck and injecting process gases that include a first gas and a second gas, and a gas supply unit supplying the process gases to the injector unit. The gas supply unit comprises first and second gas supply sources that respectively accommodate the first and second gases, first and second gas supply lines that respectively connect the first and second gas supply sources to the injector unit, and first and second heating units that are respectively disposed on the first and second gas supply lines. The first heating units disposed on the first gas supply line have a density per unit length greater than the density per unit length of the second heating units disposed on the second gas supply line.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: February 19, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Keum Seok Park, Sunjung Kim, Yihwan Kim
  • Patent number: 10170622
    Abstract: A semiconductor device has a silicide source/drain region is fabricated by growing silicon on an epitaxial region including silicon and either germanium or carbon. In the method, a gate electrode is formed on a semiconductor substrate with a gate insulating layer interposed therebetween. An epitaxial layer is formed in the semiconductor substrate at both sides of the gate electrodes. A silicon layer is formed to cap the epitaxial layer. The silicon layer and a metal material are reacted to form a silicide layer. In a PMOS, the epitaxial layer has a top surface and inclined side surfaces that are exposed above the upper surface of the active region. The silicon layer is grown on the epitaxial layer in such a way as to cap the top and inclined surfaces.
    Type: Grant
    Filed: June 12, 2017
    Date of Patent: January 1, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sungkwan Kang, Keum Seok Park, Byeongchan Lee, Sangbom Kang, Nam-Kyu Kim
  • Publication number: 20180355510
    Abstract: A semiconductor process chamber includes a susceptor, a base plate surrounding the susceptor, a liner on an inner sidewall of the base plate, and a preheat ring between the susceptor and the base plate and coplanar with the susceptor. The process chamber further includes an upper dome coupled to the base plate and covering an upper surface of the susceptor. The upper dome includes a first section on an upper surface of the base plate and a second section extending from the first section and overlapping the susceptor. The first section includes a first region on the upper surface of the base plate, a second region extending from the first region past the base plate, and a third region extending from the second region with a decreasing thickness to contact the second section.
    Type: Application
    Filed: January 12, 2018
    Publication date: December 13, 2018
    Inventors: Keum Seok Park, Gyeom Kim, Yi Hwan Kim, Sun Jung Kim, Pan Kwi Park, Jeong Ho Yoo
  • Publication number: 20180266017
    Abstract: Disclosed is a substrate treating apparatus comprising a wafer chuck on which a substrate is placed, an injector unit on a side of the wafer chuck and injecting process gases that include a first gas and a second gas, and a gas supply unit supplying the process gases to the injector unit. The gas supply unit comprises first and second gas supply sources that respectively accommodate the first and second gases, first and second gas supply lines that respectively connect the first and second gas supply sources to the injector unit, and first and second heating units that are respectively disposed on the first and second gas supply lines. The first heating units disposed on the first gas supply line have a density per unit length greater than the density per unit length of the second heating units disposed on the second gas supply line.
    Type: Application
    Filed: July 31, 2017
    Publication date: September 20, 2018
    Inventors: KEUM SEOK PARK, SUNJUNG KIM, YIHWAN KIM
  • Patent number: 9972701
    Abstract: A semiconductor device includes a fin-type active area, nanosheets, a gate, a source/drain region, and insulating spacers. The fin-type active area protrudes from a substrate in a first direction. The nanosheets are spaced from an upper surface of the fin-type active area and include channel regions. The gate is over the fin-type active area. The source/drain region is connected to the nanosheets. The insulating spacers are in the fin-type active area and between the nanosheets. Air spaces are between the insulating spacers and the source/drain region based on positions of the insulating spacers.
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: May 15, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-woo Kim, Hyun-jung Lee, Sun-jung Kim, Seung-hun Lee, Keum-seok Park, Edward Namkyu Cho
  • Publication number: 20180025901
    Abstract: A precleaning apparatus includes a chamber having an internal space in which a substrate is cleaned, a substrate support disposed in the chamber and configured to support the substrate, a plasma generation unit disposed in the chamber and configured to generate plasma gas, a heating unit configured to heat the substrate on the substrate support, a cleaning gas supply unit configured to supply gas for oxide etching to the internal space of the chamber, and a hydrogen gas supply unit configured to supply hydrogen gas to the internal space of the chamber.
    Type: Application
    Filed: January 26, 2017
    Publication date: January 25, 2018
    Inventors: Keum Seok Park, Sun Jung Kim, Yi Hwan Kim, Pan Kwi Park, Dong Suk Shin, Hyun Kwan Yu, Seung Hun Lee
  • Publication number: 20170278967
    Abstract: A semiconductor device has a silicide source/drain region is fabricated by growing silicon on an epitaxial region including silicon and either germanium or carbon. In the method, a gate electrode is formed on a semiconductor substrate with a gate insulating layer interposed therebetween. An epitaxial layer is formed in the semiconductor substrate at both sides of the gate electrodes. A silicon layer is formed to cap the epitaxial layer. The silicon layer and a metal material are reacted to form a silicide layer. In a PMOS, the epitaxial layer has a top surface and inclined side surfaces that are exposed above the upper surface of the active region. The silicon layer is grown on the epitaxial layer in such a way as to cap the top and inclined surfaces.
    Type: Application
    Filed: June 12, 2017
    Publication date: September 28, 2017
    Inventors: Sungkwan Kang, Keum Seok Park, Byeongchan Lee, Sangbom Kang, Nam-Kyu Kim
  • Publication number: 20170250261
    Abstract: A semiconductor device includes a fin-type active area, nanosheets, a gate, a source/drain region, and insulating spacers. The fin-type active area protrudes from a substrate in a first direction. The nanosheets are spaced from an upper surface of the fin-type active area and include channel regions. The gate is over the fin-type active area. The source/drain region is connected to the nanosheets. The insulating spacers are in the fin-type active area and between the nanosheets. Air spaces are between the insulating spacers and the source/drain region based on positions of the insulating spacers.
    Type: Application
    Filed: February 27, 2017
    Publication date: August 31, 2017
    Inventors: Dong-woo KIM, Hyun-jung LEE, Sun-jung KIM, Seung-hun LEE, Keum-seok PARK, Edward Namkyu CHO
  • Publication number: 20170092767
    Abstract: A semiconductor device includes an active pattern protruding from a substrate, a gate structure crossing over the active pattern, and source/drain regions disposed on the active pattern at opposite sides of the gate structure. Each of the source/drain regions includes a first epitaxial pattern contacting the active pattern and a second epitaxial pattern on the first epitaxial pattern. The first epitaxial pattern comprises a material having a lattice constant which is the same as that of the substrate, and the second epitaxial pattern comprises a material having a lattice constant greater than that of the first epitaxial pattern.
    Type: Application
    Filed: December 14, 2016
    Publication date: March 30, 2017
    Inventors: Keum Seok PARK, Jungho YOO, Jinyeong JOE, Bonyoung KOO, Dongsuk SHIN, Hongsik YOON, Byeongchan LEE
  • Patent number: 9553190
    Abstract: A semiconductor device includes an active pattern protruding from a substrate, a gate structure crossing over the active pattern, and source/drain regions disposed on the active pattern at opposite sides of the gate structure. Each of the source/drain regions includes a first epitaxial pattern contacting the active pattern and a second epitaxial pattern on the first epitaxial pattern. The first epitaxial pattern comprises a material having a lattice constant which is the same as that of the substrate, and the second epitaxial pattern comprises a material having a lattice constant greater than that of the first epitaxial pattern.
    Type: Grant
    Filed: March 30, 2015
    Date of Patent: January 24, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Keum Seok Park, Jungho Yoo, Jinyeong Joe, Bonyoung Koo, Dongsuk Shin, Hongsik Yoon, Byeongchan Lee
  • Publication number: 20160133748
    Abstract: A semiconductor device has a silicide source/drain region is fabricated by growing silicon on an epitaxial region including silicon and either germanium or carbon. In the method, a gate electrode is formed on a semiconductor substrate with a gate insulating layer interposed therebetween. An epitaxial layer is formed in the semiconductor substrate at both sides of the gate electrodes. A silicon layer is formed to cap the epitaxial layer. The silicon layer and a metal material are reacted to form a silicide layer. In a PMOS, the epitaxial layer has a top surface and inclined side surfaces that are exposed above the upper surface of the active region. The silicon layer is grown on the epitaxial layer in such a way as to cap the top and inclined surfaces.
    Type: Application
    Filed: January 14, 2016
    Publication date: May 12, 2016
    Inventors: Sungkwan Kang, Keum Seok Park, Byeongchan Lee, Sangbom Kang, Nam-Kyu Kim
  • Publication number: 20150380553
    Abstract: A semiconductor device includes an active pattern protruding from a substrate, a gate structure crossing over the active pattern, and source/drain regions disposed on the active pattern at opposite sides of the gate structure. Each of the source/drain regions includes a first epitaxial pattern contacting the active pattern and a second epitaxial pattern on the, first epitaxial pattern. The first epitaxial pattern comprises a material having a lattice constant which is the same as that of the substrate, and the second epitaxial pattern comprises a material having a lattice constant greater than that of the first epitaxial pattern.
    Type: Application
    Filed: March 30, 2015
    Publication date: December 31, 2015
    Inventors: KEUM SEOK PARK, JUNGHO YOO, JINYEONG JOE, BONYOUNG KOO, DONGSUK SHIN, HONGSIK YOON, BYEONGCHAN LEE
  • Patent number: 9112015
    Abstract: In a semiconductor device and a method of manufacturing the same, the semiconductor device includes a gate structure crossing an active region of a silicon substrate. Spacers are provided on both sides of the gate structure, respectively. Silicon patterns fill up recessed portions of the silicon substrate and on both sides of the spacers and has a shape protruding higher than a bottom surface of the gate structure, a lower edge of the protruded portion partially makes contact with a top surface of the isolation region, a first side and a second side of each of the silicon patterns, which are opposite to each other in a channel width direction in the gate structure, are inclined toward an inside of the active region. A highly doped impurity region is provided in the silicon patterns and doped with an N type impurity. The semiconductor device represents superior threshold voltage characteristics.
    Type: Grant
    Filed: June 19, 2013
    Date of Patent: August 18, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Keum-Seok Park, Jung-Ho Yoo, Woo-Bin Song, Byeong-Chan Lee
  • Publication number: 20150031183
    Abstract: A semiconductor device has a silicide source/drain region is fabricated by growing silicon on an epitaxial region including silicon and either germanium or carbon. In the method, a gate electrode is formed on a semiconductor substrate with a gate insulating layer interposed therebetween. An epitaxial layer is formed in the semiconductor substrate at both sides of the gate electrodes. A silicon layer is formed to cap the epitaxial layer. The silicon layer and a metal material are reacted to form a silicide layer. In a PMOS, the epitaxial layer has a top surface and inclined side surfaces that are exposed above the upper surface of the active region. The silicon layer is grown on the epitaxial layer in such a way as to cap the top and inclined surfaces.
    Type: Application
    Filed: September 12, 2014
    Publication date: January 29, 2015
    Inventors: Sungkwan Kang, Keum Seok Park, Byeongchan Lee, Sangbom Kang, Nam-Kyu Kim