Patents by Inventor Keun HEO
Keun HEO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240079496Abstract: A negative differential resistance device includes a dielectric layer having a first surface and a second surface opposing the first surface, a first semiconductor layer that includes a first degenerated layer that is on the first surface of the dielectric layer and has a first polarity, a second semiconductor layer that includes a second degenerated layer that has a region that overlaps the first semiconductor layer and has a second polarity, a first electrode electrically connected to the first semiconductor layer, a second electrode electrically connected to the second semiconductor layer, and a third electrode on the second surface of the dielectric layer and which has a region overlapping at least one of the first semiconductor layer or the second semiconductor layer.Type: ApplicationFiled: April 27, 2023Publication date: March 7, 2024Applicants: SAMSUNG ELECTRONICS CO., LTD., RESEARCH & BUSINESS FOUNDATION SUNGKYUNKWAN UNIVERSITYInventors: Kilsu JUNG, Jin-Hong PARK, Keun HEO, Sungjun KIM
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Patent number: 11922298Abstract: A neuron device is described. The neuron device is based on spontaneous polarization switching which includes a plurality of gate electrodes, a plurality of drain electrodes, a plurality of source lines, a dielectric layer, and a semiconductor layer. The gate electrodes are arranged parallel to each other. The drain electrodes are arranged parallel to each other. The source lines are arranged between the gate electrodes and the drain electrodes and parallel to each other. The dielectric layer is formed at intersections between the gate electrodes and the source lines. The semiconductor layer is formed at intersections between the drain electrodes and the source electrodes. The drain electrodes function as synapse-after-neuron linking terminals. The gate electrodes adjust an arrangement direction of electrical dipoles of the dielectric layer to control a firing time point and a firing height of the neuron device.Type: GrantFiled: April 27, 2020Date of Patent: March 5, 2024Assignees: SAMSUNG ELECTRONICS CO., LTD., RESEARCH & BUSINESS FOUNDATION SUNKYUNKWAN UNIVERSITYInventors: Jinhong Park, Sungjun Kim, Keun Heo, Hyeongjun Kim, Seyong Oh
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Publication number: 20240067668Abstract: The present invention relates to a heteroaryl derivative compound and a use thereof. Since the heteroaryl derivative of the present invention exhibits excellent inhibitory activity against EGFR, the heteroaryl derivative can be usefully used as a therapeutic agent for EGFR-associated diseases.Type: ApplicationFiled: December 29, 2021Publication date: February 29, 2024Inventors: Yi Kyung Ko, Ah Reum Han, Jin Hee Park, Yeong Deok Lee, Hye Rim Im, Kyun Eun Kim, Dong Keun Hwang, Su Been Nam, Myung Hoe Heo, Se Rin Cho, Eun Hwa Ko, Sung Hwan Kim, Hwan Geun Choi
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Patent number: 11670714Abstract: A negative differential resistance device includes a dielectric layer having a first surface and a second surface opposing the first surface, a first semiconductor layer that includes a first degenerated layer that is on the first surface of the dielectric layer and has a first polarity, a second semiconductor layer that includes a second degenerated layer that has a region that overlaps the first semiconductor layer and has a second polarity, a first electrode electrically connected to the first semiconductor layer, a second electrode electrically connected to the second semiconductor layer, and a third electrode on the second surface of the dielectric layer and which has a region overlapping at least one of the first semiconductor layer or the second semiconductor layer.Type: GrantFiled: June 3, 2021Date of Patent: June 6, 2023Inventors: Kilsu Jung, Jin-Hong Park, Keun Heo, Sungjun Kim
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Publication number: 20220384500Abstract: A photodetector includes a gate electrode extending in a first direction, a ferroelectric layer on the gate electrode and maintaining a state of polarization formed by a gate voltage applied to the gate electrode, a light absorbing layer on the ferroelectric layer and extending in a second direction intersecting the gate electrode, the light absorbing layer including a two-dimensional (2D) material of a layered structure, a source electrode on the ferroelectric layer and connected to a first end of the light absorbing layer, and a drain electrode on the ferroelectric layer and connected to the a second end of the light absorbing layer.Type: ApplicationFiled: February 10, 2022Publication date: December 1, 2022Applicant: RESEARCH & BUSINESS FOUNDATION SUNGKYUNKWAN UNIVERSITYInventors: Sungjun KIM, Jin-Hong PARK, Sunghun LEE, Keun HEO
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Patent number: 11489041Abstract: A semiconductor device according to an embodiment may include a board, an insulation layer disposed on the board, a threshold voltage control layer disposed on the insulation layer, a first semiconductor layer disposed on the threshold voltage control layer, and a second semiconductor layer disposed on the threshold voltage control layer to cover a portion of the first semiconductor layer. A negative differential resistance device according to an embodiment has an advantageous effect in that the gate voltage enables a peak voltage to be freely controlled within an operation range of the device by forming the threshold voltage control layer.Type: GrantFiled: June 30, 2020Date of Patent: November 1, 2022Assignee: Research & Business Foundation Sungkyunkwan UniversityInventors: Jin Hong Park, Kil Su Jung, Keun Heo, Sung Jun Kim
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Patent number: 11437572Abstract: Provided is a negative differential resistance element having a 3-dimension vertical structure. The negative differential resistance element having a 3-dimension vertical structure includes: a substrate; a first electrode that is formed on the substrate to receive a current; a second semiconductor material that is formed in some region of the substrate; a first semiconductor material that is deposited in some other region and the first electrode of the substrate and some region of an upper end of the second semiconductor material; an insulator that has a part vertically erected from the substrate, the other part vertically erected from the second semiconductor material, and an upper portion stacked with a first semiconductor material; and a second electrode that is formed at an upper end of the second semiconductor material to output a current, thereby significantly reducing an area of the device and greatly improving device scaling and integration.Type: GrantFiled: May 11, 2020Date of Patent: September 6, 2022Assignee: Research & Business Foundation Sungkyunkwan UniversityInventors: Jin Hong Park, Kil Su Jung, Keun Heo
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Publication number: 20220093803Abstract: A negative differential resistance device includes a dielectric layer having a first surface and a second surface opposing the first surface, a first semiconductor layer that includes a first degenerated layer that is on the first surface of the dielectric layer and has a first polarity, a second semiconductor layer that includes a second degenerated layer that has a region that overlaps the first semiconductor layer and has a second polarity, a first electrode electrically connected to the first semiconductor layer, a second electrode electrically connected to the second semiconductor layer, and a third electrode on the second surface of the dielectric layer and which has a region overlapping at least one of the first semiconductor layer or the second semiconductor layer.Type: ApplicationFiled: June 3, 2021Publication date: March 24, 2022Applicants: SAMSUNG ELECTRONICS CO., LTD., RESEARCH & BUSINESS FOUNDATION SUNGKYUNKWAN UNIVERSITYInventors: Kilsu JUNG, Jin-Hong PARK, Keun HEO, Sungjun KIM
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Patent number: 11276761Abstract: A semiconductor device includes at least one trench extending into a semiconductor substrate and lined with a gate dielectric layer; a dipole inducing layer covering a lowermost portion of the lined trench; a gate electrode covering the dipole inducing layer and filled in the lined trench; and doping regions, in the semiconductor substrate, separated from each other by the lined trench and separated from the dipole inducing layer.Type: GrantFiled: January 6, 2020Date of Patent: March 15, 2022Assignee: SK hynix Inc.Inventors: Dong-Soo Kim, Sung-Won Lim, Eun-Jeong Kim, Hyun-Jin Chang, Keun Heo, Jee-Hyun Kim
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Publication number: 20210005710Abstract: A semiconductor device according to an embodiment may include a board, an insulation layer disposed on the board, a threshold voltage control layer disposed on the insulation layer, a first semiconductor layer disposed on the threshold voltage control layer, and a second semiconductor layer disposed on the threshold voltage control layer to cover a portion of the first semiconductor layer. A negative differential resistance device according to an embodiment has an advantageous effect in that the gate voltage enables a peak voltage to be freely controlled within an operation range of the device by forming the threshold voltage control layer.Type: ApplicationFiled: June 30, 2020Publication date: January 7, 2021Applicant: Research & Business Foundation Sungkyunkwan UniversityInventors: Jin Hong PARK, Kil Su JUNG, Keun HEO, Sung Jun KIM
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Publication number: 20200357988Abstract: Provided is a negative differential resistance element having a 3-dimension vertical structure. The negative differential resistance element having a 3-dimension vertical structure includes: a substrate; a first electrode that is formed on the substrate to receive a current; a second semiconductor material that is formed in some region of the substrate; a first semiconductor material that is deposited in some other region and the first electrode of the substrate and some region of an upper end of the second semiconductor material; an insulator that has a part vertically erected from the substrate, the other part vertically erected from the second semiconductor material, and an upper portion stacked with a first semiconductor material; and a second electrode that is formed at an upper end of the second semiconductor material to output a current, thereby significantly reducing an area of the device and greatly improving device scaling and integration.Type: ApplicationFiled: May 11, 2020Publication date: November 12, 2020Applicant: Research & Business Foundation Sungkyunkwan UniversityInventors: Jin Hong PARK, Kil Su JUNG, Keun HEO
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Publication number: 20200342300Abstract: A neuron device is described. The neuron device is based on spontaneous polarization switching which includes a plurality of gate electrodes, a plurality of drain electrodes, a plurality of source lines, a dielectric layer, and a semiconductor layer. The gate electrodes are arranged parallel to each other. The drain electrodes are arranged parallel to each other. The source lines are arranged between the gate electrodes and the drain electrodes and parallel to each other. The dielectric layer is formed at intersections between the gate electrodes and the source lines. The semiconductor layer is formed at intersections between the drain electrodes and the source electrodes. The drain electrodes function as synapse-after-neuron linking terminals. The gate electrodes adjust an arrangement direction of electrical dipoles of the dielectric layer to control a firing time point and a firing height of the neuron device.Type: ApplicationFiled: April 27, 2020Publication date: October 29, 2020Applicant: Research & Business Foundation Sungkyunkwan UniversityInventors: Jinhong PARK, Sungjun KIM, Keun HEO, Hyeongjun KIM, Seyong OH
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Publication number: 20200152754Abstract: A semiconductor device includes at least one trench extending into a semiconductor substrate and lined with a gate dielectric layer; a dipole inducing layer covering a lowermost portion of the lined trench; a gate electrode covering the dipole inducing layer and filled in the lined trench; and doping regions, in the semiconductor substrate, separated from each other by the lined trench and separated from the dipole inducing layer.Type: ApplicationFiled: January 6, 2020Publication date: May 14, 2020Inventors: Dong-Soo KIM, Sung-Won LIM, Eun-Jeong KIM, Hyun-Jin CHANG, Keun HEO, Jee-Hyun KIM
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Patent number: 10559626Abstract: A neuromorphic device is provided. The neuromorphic device may include a pre-synaptic neuron; a row line extending in a row direction from the pre-synaptic neuron; a post-synaptic neuron; a column line extending in a column direction from the post-synaptic neuron; and a synapse disposed at an intersection between the row line and the column line. The synapse may include a first synapse layer including a plurality of first carbon nano-tubes; a second synapse layer including a plurality of second carbon nano-tubes having different structures from the plurality of first carbon nano-tubes; and a third synapse layer including a plurality of third carbon nano-tubes having different structures from the plurality of first carbon nano-tubes and the plurality of second carbon nano-tubes.Type: GrantFiled: July 12, 2017Date of Patent: February 11, 2020Assignee: SK hynix Inc.Inventors: Yong-Soo Choi, Keun Heo, Hyung-Dong Lee
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Patent number: 10553692Abstract: A semiconductor device includes at least one trench extending into a semiconductor substrate and lined with a gate dielectric layer; a dipole inducing layer covering a lowermost portion of the lined trench; a gate electrode covering the dipole inducing layer and filled in the lined trench; and doping regions, in the semiconductor substrate, separated from each other by the lined trench and separated from the dipole inducing layer.Type: GrantFiled: July 12, 2016Date of Patent: February 4, 2020Assignee: SK hynix Inc.Inventors: Dong-Soo Kim, Sung-Won Lim, Eun-Jeong Kim, Hyun-Jin Chang, Keun Heo, Jee-Hyun Kim
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Patent number: 10254975Abstract: Apparatuses having variable communication speeds are disclose. In one example, an apparatus may comprise a controller configured to: receive a signal from a host, the signal being compatible with a data communication protocol at a first data communication speed; selectively implement a first data communication protocol from a plurality of data communication protocols to communicate with a first memory or implement a second data communication protocol from the plurality of data communication protocols to communicate with a second memory based on the data communication speed; store data in the first memory via the first data communication protocol when the data communication speed is a first speed; and store data in the second memory via the second data communication protocol when the data communication speed is a second speed that is different than the first speed.Type: GrantFiled: June 20, 2016Date of Patent: April 9, 2019Assignee: Seagate Technology IncorporatedInventors: Keun Heo, Byung Wook Kim, Young Min Ku
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Publication number: 20180240846Abstract: A neuromorphic device is provided. The neuromorphic device may include a pre-synaptic neuron; a row line extending in a row direction from the pre-synaptic neuron; a post-synaptic neuron; a column line extending in a column direction from the post-synaptic neuron; and a synapse disposed at an intersection between the row line and the column line. The synapse may include a first synapse layer including a plurality of first carbon nano-tubes; a second synapse layer including a plurality of second carbon nano-tubes having different structures from the plurality of first carbon nano-tubes; and a third synapse layer including a plurality of third carbon nano-tubes having different structures from the plurality of first carbon nano-tubes and the plurality of second carbon nano-tubes.Type: ApplicationFiled: July 12, 2017Publication date: August 23, 2018Inventors: Yong-Soo CHOI, Keun HEO, Hyung-Dong LEE
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Publication number: 20170186844Abstract: A semiconductor device includes at least one trench extending into a semiconductor substrate and lined with a gate dielectric layer; a dipole inducing layer covering a lowermost portion of the lined trench; a gate electrode covering the dipole inducing layer and filled in the lined trench; and doping regions, in the semiconductor substrate, separated from each other by the lined trench and separated from the dipole inducing layer.Type: ApplicationFiled: July 12, 2016Publication date: June 29, 2017Inventors: Dong-Soo KIM, Sung-Won LIM, Eun-Jeong KIM, Hyun-Jin CHANG, Keun HEO, Jee-Hyun KIM
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Publication number: 20160371018Abstract: Apparatuses having variable communication speeds are disclose. In one example, an apparatus may comprise a controller configured to: receive a signal from a host, the signal being compatible with a data communication protocol at a first data communication speed; selectively implement a first data communication protocol from a plurality of data communication protocols to communicate with a first memory or implement a second data communication protocol from the plurality of data communication protocols to communicate with a second memory based on the data communication speed; store data in the first memory via the first data communication protocol when the data communication speed is a first speed; and store data in the second memory via the second data communication protocol when the data communication speed is a second speed that is different than the first speed.Type: ApplicationFiled: June 20, 2016Publication date: December 22, 2016Applicant: Seagate Technology LLCInventors: Keun HEO, Byung Wook KIM, Young Min KU
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Patent number: 9372625Abstract: Apparatuses having variable communication speeds are disclose. In one example, an apparatus may comprise a controller configured to: receive a signal from a host, the signal being compatible with a data communication protocol at a first data communication speed; selectively implement a first data communication protocol from a plurality of data communication protocols to communicate with a first memory or implement a second data communication protocol from the plurality of data communication protocols to communicate with a second memory based on the data communication speed; store data in the first memory via the first data communication protocol when the data communication speed is a first speed; and store data in the second memory via the second data communication protocol when the data communication speed is a second speed that is different than the first speed.Type: GrantFiled: March 26, 2013Date of Patent: June 21, 2016Assignee: Seagate Technology InternationalInventors: Keun Heo, Byung Wook Kim, Young Min Ku