Abstract: The present invention relates to a composition for preventing or treating transplantation rejection or a transplantation rejection disease, comprising a novel compound and a calcineurin inhibitor. A co-administration of the present invention 1) reduces the activity of pathogenic Th1 cells or Th17 cells, 2) increases the activity of Treg cells, 3) has an inhibitory effect against side effects, such as tissue damage, occurring in the sole administration thereof, 4) inhibits various pathogenic pathways, 5) inhibits the cell death of inflammatory cells, and 6) increases the activity of mitochondria, in an in vivo or in vitro allogenic model, a transplantation rejection disease model, a skin transplantation model, and a liver-transplanted patient, and thus inhibits transplantation rejection along with mitigating side effects possibly occurring in the administration of a conventional immunosuppressant alone.

Abstract: The present disclosure relates to a polycarbonate resin composition, and more particularly, to a polycarbonate resin composition containing 90 wt % to 99 wt % of a polycarbonate resin, 0.3 wt % to 0.7 wt % of an anthraquinone-based black dye, and 0.2 wt % to 1.0 wt % of an acrylic polymeric chain extender, and a molded article containing the same.

Abstract: The present technology includes a storage device including a memory device including a first storage region and a second storage region and a memory controller configured to, in response to a write request in the first storage region from an external host, acquire data stored the first region based on a fail prediction information provided from the memory device and to perform a write operation corresponding to the write request, wherein the first storage region and the second storage region are allocated according to logical addresses of data to be stored in by requests of the external host.

Abstract: The present technology includes a storage device including a memory device including a first storage region and a second storage region and a memory controller configured to, in response to a write request in the first storage region from an external host, acquire data stored the first region based on a fail prediction information provided from the memory device and to perform a write operation corresponding to the write request, wherein the first storage region and the second storage region are allocated according to logical addresses of data to be stored in by requests of the external host.

Abstract: A storage device having improved data recovery performance includes a memory device including a first storage region and a second storage region, and a memory controller that controls the memory device. Before performing a write operation in the first storage region, the memory controller may backup data previously stored in the first storage region, based on a fail probability of the write operation to be performed in the first storage region. If the write operation fails, the previously-stored data may be recovered from where it was backed up.

Abstract: A storage device having improved data recovery performance includes a memory device including a first storage region and a second storage region, and a memory controller that controls the memory device. Before performing a write operation in the first storage region, the memory controller may backup data previously stored in the first storage region, based on a fail probability of the write operation to be performed in the first storage region. If the write operation fails, the previously-stored data may be recovered from where it was backed up.

Abstract: Provided is an apparatus for providing external panoramic view contents for an aircraft during flight by installing a plurality of cameras in a plurality of windows installed in an aircraft for displaying external panoramic views inside the aircraft while the aircraft flies in order for aircraft passengers to enjoy them. The apparatus includes a shooting unit having a plurality of cameras for shooting aircraft's external panoramic views; a control unit for receiving a plurality of images from the cameras and processing them; and a display unit comprising a single display and a multi-display including a plurality of sub-displays.

Abstract: The present technology includes a storage device including a memory device including a first storage region and a second storage region and a memory controller configured to, in response to a write request in the first storage region from an external host, acquire data stored the first region based on a fail prediction information provided from the memory device and to perform a write operation corresponding to the write request, wherein the first storage region and the second storage region are allocated according to logical addresses of data to be stored in by requests of the external host.

Abstract: Provided is an apparatus for providing external panoramic view contents for an aircraft during flight by installing a plurality of cameras in a plurality of windows installed in an aircraft for displaying external panoramic views inside the aircraft while the aircraft flies in order for aircraft passengers to enjoy them. The apparatus includes a shooting unit having a plurality of cameras for shooting aircraft's external panoramic views; a control unit for receiving a plurality of images from the cameras and processing them; and a display unit comprising a single display and a multi-display including a plurality of sub-displays.

Abstract: A nonvolatile memory device and a method of operating the same include a memory block, a controller interface unit, and a memory control unit. The nonvolatile memory device is configured to receive through the controller interface unit from a controller an erase command for performing an erase operation on the memory block. The memory control unit configured to perform the erase operation on the memory block in response to the nonvolatile memory device receiving the erase command. When the nonvolatile memory device receives an erase suspend command through the controller interface unit from the controller during the erase operation, the memory control unit continues performing the erase operation up to a specified time after the erase suspend command is received before suspending the erase operation in response to receiving the erase suspend command.

Abstract: A memory system includes: a memory device comprising a plurality of dies each die comprising a plurality of planes, each plane comprising a plurality of blocks, each block comprising a plurality of pages; a controller suitable for inputting a plurality of commands received from a host to the memory device through command queuing, wherein a first memory die among the plurality of memory dies processes the plurality of commands as a burst command, and performs command operations in one or more pages in one or more first memory blocks included in the first memory die, and data corresponding to the command operations are stored in a plurality of latches corresponding to the one or more first memory blocks.

Abstract: A memory device may include a memory region, and a control unit for performing an internal operation on the memory region in response to a command received from an external device, and in a wait state in connection with the performance of the internal operation, which depends on the internal operation.

Abstract: A memory system includes: a memory device comprising a plurality of dies each die comprising a plurality of planes, each plane comprising a plurality of blocks, each block comprising a plurality of pages; a controller suitable for inputting a plurality of commands received from a host to the memory device through command queuing, wherein a first memory die among the plurality of memory dies processes the plurality of commands as a burst command, and performs command operations in one or more pages in one or more first memory blocks included in the first memory die, and data corresponding to the command operations are stored in a plurality of latches corresponding to the one or more first memory blocks.

Abstract: A system in package (SIP) semiconductor system includes a memory device, a controller, a first input/output terminal, a test control unit, and a second input/output terminal. The controller communicates with the memory device. The first input/output terminal performs communication between the controller and a device external to the SIP semiconductor system. The test control unit controls a predetermined test mode of the memory device. The second input/output terminal performs communication between the test control unit and at least the device external to the SIP semiconductor system.

Abstract: A system in package (SIP) semiconductor system includes a memory device, a controller, a first input/output terminal, a test control unit, and a second input/output terminal. The controller communicates with the memory device. The first input/output terminal performs communication between the controller and a device external to the SIP semiconductor system. The test control unit controls a predetermined test mode of the memory device. The second input/output terminal performs communication between the test control unit and at least the device external to the SIP semiconductor system.