Abstract: A semiconductor device includes a control circuit configured to generate an input enable signal, an output enable signal, a latch control signal, and an error correction control signal based on a write control signal, a write check command, and a read check command for performing an error correction test mode; a latch circuit configured to generate latch data, a latch parity, and a latch masking signal by latching input data, an input parity, and an input masking signal and configured to re-store corrected data as the latch data, during a period in which the latch control signal is enabled; and an error correction circuit configured to generate the corrected data by correcting an error, included in the latch data, based on the latch data, the latch parity and the latch masking signal during a period in which the error correction control signal is enabled.

Abstract: A semiconductor device includes a control circuit configured to generate an input enable signal, an output enable signal, a latch control signal, and an error correction control signal based on a write control signal, a write check command, and a read check command for performing an error correction test mode; a latch circuit configured to generate latch data, a latch parity, and a latch masking signal by latching input data, an input parity, and an input masking signal and configured to re-store corrected data as the latch data, during a period in which the latch control signal is enabled; and an error correction circuit configured to generate the corrected data by correcting an error, included in the latch data, based on the latch data, the latch parity and the latch masking signal during a period in which the error correction control signal is enabled.

Abstract: An internal voltage generation circuit includes: a selection unit configured to select one of first and second reference voltages as a selection reference voltage in response to a self refresh signal and a power-down mode signal and output the selection reference voltage; a driving signal generation unit configured to compare the selection reference voltage with a negative word line voltage applied to an unselected word line and generate a driving signal; and a driving unit configured to change the negative word line voltage in response to the driving signal.

Abstract: A semiconductor memory device includes a first core region and a second core region disposed along a first reference line parallel to a major axis, the first reference line connecting an input pad and an output pad; first and second cell blocks disposed in the first core region along the first reference line; third and fourth cell blocks disposed in the second core region along the first reference line; and a repeater positioned between the third and fourth cell blocks, and configured to receive data outputted from the first cell block or the second cell block, amplify the received data and transfer the amplified data to a second global input/output line. Reducing the number of needed global input/output lines leads to layout area reduction. Moreover, since repeaters are driven in read operations for a limited number of cell blocks, signal gain may be reduced, thus reducing overall power consumption.

Abstract: A semiconductor memory device includes an all bank select signal generation block configured to receive level signals including information on at least one bank which has been refreshed, and generate all bank select signals, in response to an all bank refresh command; and a bank block including a plurality of banks which are configured to be refreshed in response to the all bank select signals or are refreshed in response to per bank select signals which are enabled when the level signals are enabled.

Abstract: There is provided a command generation circuit. The command generation circuit includes a first driving unit driving an output node in response to an internal MRS command and a RAS idle signal; a second driving unit driving the output node in response to an off-signal; and a latch unit latching a signal at the output node in response to a power-up signal and generating an SRR command.

Abstract: A semiconductor memory device includes a temperature sensor configured to generate a low-temperature signal which is enabled at below first set temperature and a high-temperature signal which is enabled at above second set temperature; a start signal generator configured to receive a refresh command and generate a start signal according to the low-temperature signal; and an address counter configured to count refresh addresses in response to the start signal.

Abstract: A semiconductor memory device includes a first core region and a second core region disposed along a first reference line parallel to a major axis, the first reference line connecting an input pad and an output pad; first and second cell blocks disposed in the first core region along the first reference line; third and fourth cell blocks disposed in the second core region along the first reference line; and a repeater positioned between the third and fourth cell blocks, and configured to receive data outputted from the first cell block or the second cell block, amplify the received data and transfer the amplified data to a second global input/output line. Reducing the number of needed global input/output lines leads to layout area reduction. Moreover, since repeaters are driven in read operations for a limited number of cell blocks, signal gain may be reduced, thus reducing overall power consumption.

Abstract: A semiconductor memory device includes an all bank select signal generation block configured to receive level signals including information on at least one bank which has been refreshed, and generate all bank select signals, in response to an all bank refresh command; and a bank block including a plurality of banks which are configured to be refreshed in response to the all bank select signals or are refreshed in response to per bank select signals which are enabled when the level signals are enabled.

Abstract: An internal voltage generation circuit includes: a selection unit configured to select one of first and second reference voltages as a selection reference voltage in response to a self refresh signal and a power-down mode signal and output the selection reference voltage; a driving signal generation unit configured to compare the selection reference voltage with a negative word line voltage applied to an unselected word line and generate a driving signal; and a driving unit configured to change the negative word line voltage in response to the driving signal.

Abstract: A fuse circuit includes a fuse information signal generation unit and an output driving unit. The fuse information signal generation unit is configured to precharge a fuse information signal in response to a precharge signal and drive the fuse information signal in response to a selection signal capable of cutting a fuse. The output driving unit configured to equally maintain potentials at both terminals of the fuse in response to a control signal.

Abstract: A driving controller for use in stabilizing transient voltages from power supplies is presented. The driving controller includes a first pulse generator, a second pulse generator, and a control signal generator. The first pulse generator is configured to generate a power-up pulse signal including a pulse activating at a time of terminating a power-up period. The second pulse generator is configured to generate a detection pulse signal including a pulse that is being active from a time when an internal voltage reaches a predetermined level. The control signal generator is configured to generate an operation control signal, which controls a driving controller activating the internal voltage, in response to the power-up pulse signal and the detection pulse signal.

Abstract: A semiconductor memory device includes a temperature sensor configured to generate a low-temperature signal which is enabled at below first set temperature and a high-temperature signal which is enabled at above second set temperature; a start signal generator configured to receive a refresh command and generate a start signal according to the low-temperature signal; and an address counter configured to count refresh addresses in response to the start signal.

Abstract: A semiconductor memory device includes: a command input unit configured to receive a plurality of external commands in synchronization with a rising edge of an internal clock to generate a plurality of pre-control signals; an output control signal generating unit configured to receive the plurality of external commands to generate an output control signal in synchronization with a falling edge of the internal clock prior to the rising edge of the internal clock; an address input unit configured to receive a plurality of addresses to output a plurality of internal addresses in response to the output control signal; and an internal driving signal generating unit configured to receive the plurality of internal addresses and the plurality of pre-control signals to generate a plurality of internal driving control signals.

Abstract: There is provided a command generation circuit. The command generation circuit includes a first driving unit driving an output node in response to an internal MRS command and a RAS idle signal; a second driving unit driving the output node in response to an off-signal; and a latch unit latching a signal at the output node in response to a power-up signal and generating an SRR command.

Abstract: There is provided a command generation circuit. The command generation circuit includes a first driving unit driving an output node in response to an internal MRS command and a RAS idle signal; a second driving unit driving the output node in response to an off-signal; and a latch unit latching a signal at the output node in response to a power-up signal and generating an SRR command.

Abstract: A fuse circuit includes a fuse information signal generation unit and an output driving unit. The fuse information signal generation unit is configured to precharge a fuse information signal in response to a precharge signal and drive the fuse information signal in response to a selection signal capable of cutting a fuse. The output driving unit configured to equally maintain potentials at both terminals of the fuse in response to a control signal.

Abstract: A fuse circuit includes a fuse, a control pulse generation unit, and an equipotential element. The fuse is coupled between a power supply voltage terminal and a first node. The control pulse generation unit is configured to generate a control pulse including a pulse generated in a period in which a power-up period is ended. The equipotential element is configured to make the first node have the same potential as a power supply voltage in response to the control pulse.

Abstract: There is provided a flag signal generation circuit. The flag signal generation circuit includes a status register read (SRR) signal generating unit receiving an idle signal and an SRR command to generate an SRR signal; a pulse signal generating unit receiving an SRR signal to generate a pulse signal; and a flag signal generating unit receiving the pulse signal and a read signal for SRR to generate a flag signal.

Abstract: Provided is a data output circuit having an output driver that outputs accurate data voltages while preventing unwanted current leakage through switching CMOS transistors. The data output circuit includes a pre-driver, an output driver and a high resistance resistor. The pre-driver is configured to pre-drive a data pulse. The output driver is configured to receive the output signal of the pre-driver. The high resistance resistor is configured to adjust the output signal of the pre-drive so that a slope of the output signal is gradual r and to provide the smoothed output signal to the output driver. The high resistance resistor is a gate resistor of a MOS transistor of the output driver.