Abstract: A nonvolatile memory apparatus may include a first memory cell array, a second memory cell array, and a data sensing circuit. The first memory cell array may include a plurality of first memory cells coupled between a plurality of first word lines and a bit line. The second memory cell array may include a plurality of second memory cells coupled between a plurality of second word lines and the bit line. The data sensing circuit may define a sensing period and a latch period based on a power-up signal, may precharge a sensing node coupled to the bit line, may sense and amplify a voltage level of the sensing node, during the sensing period, and may generate an output signal by latching the sensed and amplified signal during the latch period.

Abstract: A nonvolatile memory apparatus and an operating method of the nonvolatile memory apparatus may include a first memory cell array, a second memory cell array, a bit line switch, and a sensing control signal generation circuit. The first and second memory cell arrays may be coupled to a bit line. The bit line switch may electrically couple the first memory cell array to the second memory cell array according to an operation period of the non-volatile memory apparatus.

Abstract: A semiconductor apparatus includes a fuse array, a word line decoder, a bit line decoder, a bank information comparison circuit, and a rupture circuit. The word line decoder is configured to select a word line of the fuse array based on a bank select address signal. The bit line decoder is configured to select a bit line of the fuse array based on a fail row address signal. The bank information comparison circuit and the rupture circuit are configured to rupture a fuse coupled to the word line and the bit line when a fail bank address signal and the bank select address signal correspond to each other.

Abstract: A nonvolatile memory apparatus and an operating method of the nonvolatile memory apparatus may include a first memory cell array, a second memory cell array, a bit line switch, and a sensing control signal generation circuit. The first and second memory cell arrays may be coupled to a bit line. The bit line switch may electrically couple the first memory cell array to the second memory cell array according to an operation period of the non-volatile memory apparatus.

Abstract: A nonvolatile memory apparatus may include a first memory cell array, a second memory cell array, and a data sensing circuit. The first memory cell array may include a plurality of first memory cells coupled between a plurality of first word lines and a bit line. The second memory cell array may include a plurality of second memory cells coupled between a plurality of second word lines and the bit line. The data sensing circuit may define a sensing period and a latch period based on a power-up signal, may precharge a sensing node coupled to the bit line, may sense and amplify a voltage level of the sensing node, during the sensing period, and may generate an output signal by latching the sensed and amplified signal during the latch period.

Abstract: A semiconductor apparatus includes a fuse array, a word line decoder, a bit line decoder, a bank information comparison circuit, and a rupture circuit. The word line decoder is configured to select a word line of the fuse array based on a bank select address signal. The bit line decoder is configured to select a bit line of the fuse array based on a fail row address signal. The bank information comparison circuit and the rupture circuit are configured to rupture a fuse coupled to the word line and the bit line when a fail bank address signal and the bank select address signal correspond to each other.

Abstract: A semiconductor integrated circuit device includes a plurality of column repair address lines configured to cross and a plurality of mat select lines; a fuse set unit including a plurality of latch units electrically coupled with the plurality of column repair address lines and the plurality of mat select lines; a fuse driving unit configured to provide fuse data to the latch units through the plurality of column repair address lines; and an equalizer configured to equalize the fuse data to a same level in response to a select signal of the fuse set unit and a boot-up signal of the fuse set unit.

Abstract: A semiconductor integrated circuit device includes a plurality of column repair address lines configured to cross and a plurality of mat select lines; a fuse set unit including a plurality of latch units electrically coupled with the plurality of column repair address lines and the plurality of mat select lines; a fuse driving unit configured to provide fuse data to the latch units through the plurality of column repair address lines; and an equalizer configured to equalize the fuse data to a same level in response to a select signal of the fuse set unit and a boot-up signal of the fuse set unit.