Abstract: A semiconductor memory device having a multi-chip package structure providing active termination control. The semiconductor memory device includes first and second memory chips sharing a data I/O bus. The first memory chip includes a first chip enable (CE) port determining whether the first memory chip is activated, and a second CE port monitoring whether the second memory chip is activated. An active termination unit is turned ON only when the first and second chips are deactivated.

Abstract: Embodiments of the invention include features in the semiconductor memory device that are configured to receive command signals from a memory controller and selectively output at least a portion of the received command signals back to the memory controller for verification. Embodiments of the invention also provide methods for verifying the proper communication of command signals from a memory controller to a semiconductor memory device. Embodiments of the invention also provide systems and methods for testing memory cells in a semiconductor memory device.

Abstract: Embodiments of the invention include features in the semiconductor memory device that are configured to receive command signals from a memory controller and selectively output at least a portion of the received command signals back to the memory controller for verification. Embodiments of the invention also provide methods for verifying the proper communication of command signals from a memory controller to a semiconductor memory device. Embodiments of the invention also provide systems and methods for testing memory cells in a semiconductor memory device.