Abstract: A heterojunction bipolar transistor (HBT) and methods of fabrication provide a substrate, a base having a first lateral area, an emitter, a sub-collector having a second lateral area, and a collector above the sub-collector, wherein the second lateral area of the sub-collector is less than the first lateral area of the base, which enables the fabrication of HBTs with high linearity, as measured by an improved third order distortion (OIP3) parameter, while maintaining high gain; which enables the fabrication of HBTs with a selectively grown or overgrown collector/sub-collector; and which reduces a capacitance between the base and collector of the HBTs.

Abstract: A heterojunction bipolar transistor (HBT) and methods of fabrication provide a substrate, a base having a first lateral area, an emitter, a sub-collector having a second lateral area, and a collector above the sub-collector, wherein the second lateral area of the sub-collector is less than the first lateral area of the base, which enables the fabrication of HBTs with high linearity, as measured by an improved third order distortion (OIP3) parameter, while maintaining high gain; which enables the fabrication of HBTs with a selectively grown or overgrown collector/sub-collector; and which reduces a capacitance between the base and collector of the HBTs.

Abstract: A field effect transistor (FET) includes a substrate, a back barrier disposed on the substrate, a channel disposed on the back barrier, a front barrier disposed on the channel, a source, and a drain, such that at least one of the front barrier and the back barrier includes an anti-barrier-conduction (ABC) spacer which reduces parasitic conduction on a path from the source to the drain through at least one of the front barrier and the back barrier, reduces ON-state leakage from the channel to gate or substrate of the FET via resonant tunneling, and reduces OFF-state leakage by presenting tall barriers to electrons as well as electron-holes. This results in a highly linear, low gate leakage, low parasitic conduction, and low noise operation of FET.

Abstract: Fabrication of a dual enhancement-mode/depletion-mode (E-Mode/D-Mode) high electron mobility transistor (HEMT) called a threshold control terminal HEMT (TCT-HEMT) is performed which reduces capacitance between the TCT electrode and the source and drain electrodes of a TCT-HEMT, since such a capacitance may be parasitic, and which fabricates a TCT-HEMT capable of high-frequency operation. A method for fabricating a field-effect transistor (FET) includes: providing a substrate; disposing a back barrier on the substrate to form a base stack; forming a doped layer on the base stack; grow additional layers, including a threshold-control terminal (TCT) access layer; etch a pattern in at least one of the doped layer and the additional layers; and disposing a TCT contact on the TCT access layer.

Abstract: Embodiments of the present disclosures provide methods and apparatus for manufacturing semiconductor devices such as transistors used for amplifying or switching electronic signals. Specifically, embodiments of the present disclosure generally relate to a semiconductor device having a film stack including an interlayer of semiconductor material and a buffer layer of semiconductor material underneath an active device layer. In various embodiments, the interlayer may include group III-V semiconductor materials formed between a first surface of a silicon-based substrate and the buffer layer. In certain embodiments the buffer layer may comprise group IV semiconductor materials. The interlayer may have a lattice constant designed to mitigate lattice mismatch between the group IV buffer layer and the silicon-based substrate. The buffer layer may provide improved integration of the active device layer to improve the performance of the resulting device.

Abstract: Embodiments of the present disclosure generally relate to a film stack including layers of group III-V semiconductor materials. The film stack includes a phosphorous containing layer deposited over a silicon substrate, a GaAs containing layer deposited on the phosphorous containing layer, and an aluminum containing layer deposited on the GaAs containing layer. The GaAs containing layer between the phosphorous containing layer and the aluminum containing layer improves the surface smoothness of the aluminum containing layer.

Abstract: Embodiments described herein generally relate to a substrate processing system, such as an etch processing system. In one embodiment, a method of processing a substrate is disclosed herein. The method includes removing a native oxide from a surface of the substrate, baking the substrate in a pre-treatment thermal chamber such that double atomic steps are formed on the surface of the substrate, and forming an epitaxial layer on the substrate after the substrate is baked.

Abstract: Embodiments of the present disclosures provide methods and apparatus for manufacturing semiconductor devices such as transistors used for amplifying or switching electronic signals. Specifically, embodiments of the present disclosure generally relate to a semiconductor device having a film stack including an interlayer of semiconductor material and a buffer layer of semiconductor material underneath an active device layer. In various embodiments, the interlayer may include group III-V semiconductor materials formed between a first surface of a silicon-based substrate and the buffer layer. In certain embodiments the buffer layer may comprise group IV semiconductor materials. The interlayer may have a lattice constant designed to mitigate lattice mismatch between the group IV buffer layer and the silicon-based substrate. The buffer layer may provide improved integration of the active device layer to improve the performance of the resulting device.

Abstract: Embodiments of the present disclosures provide methods and apparatus for manufacturing semiconductor devices such as transistors used for amplifying or switching electronic signals. Specifically, embodiments of the present disclosure generally relate to a semiconductor device having a film stack including an interlayer of semiconductor material and a buffer layer of semiconductor material underneath an active device layer. In various embodiments, the interlayer may include group III-V semiconductor materials formed between a first surface of a silicon-based substrate and the buffer layer. In certain embodiments the buffer layer may comprise group IV semiconductor materials. The interlayer may have a lattice constant designed to mitigate lattice mismatch between the group IV buffer layer and the silicon-based substrate. The buffer layer may provide improved integration of the active device layer to improve the performance of the resulting device.

Abstract: Embodiments described herein generally relate to a substrate processing system, such as an etch processing system. In one embodiment, a method of processing a substrate is disclosed herein. The method includes removing a native oxide from a surface of the substrate, baking the substrate in a pre-treatment thermal chamber such that double atomic steps are formed on the surface of the substrate, and forming an epitaxial layer on the substrate after the substrate is baked.

Abstract: Embodiments of the present disclosures provide methods and apparatus for manufacturing semiconductor devices such as transistors used for amplifying or switching electronic signals. Specifically, embodiments of the present disclosure generally relate to a semiconductor device having a film stack including an interlayer of semiconductor material and a buffer layer of semiconductor material underneath an active device layer. In various embodiments, the interlayer may include group III-V semiconductor materials formed between a first surface of a silicon-based substrate and the buffer layer. In certain embodiments the buffer layer may comprise group IV semiconductor materials. The interlayer may have a lattice constant designed to mitigate lattice mismatch between the group IV buffer layer and the silicon-based substrate. The buffer layer may provide improved integration of the active device layer to improve the performance of the resulting device.

Abstract: Embodiments of the present disclosure generally relate to a semiconductor device including layers of group III-V semiconductor materials. In one embodiment, the semiconductor device includes a phosphorous containing layer deposited on a silicon substrate, wherein a lattice mismatch between the phosphorous containing layer and the silicon substrate is less than 5%, a group III-V compound nucleation layer deposited on the phosphorous containing layer at a first temperature, the group III-V compound nucleation layer having a first thickness, a group III-V compound transition layer deposited on the group III-V compound nucleation layer at a second temperature higher than the first temperature, the group III-V compound transition layer having a second thickness larger than the first thickness, and the group III-V compound nucleation layer is different from the group III-V compound transition layer, and an active layer deposited on the group III-V compound transition layer.

Abstract: Embodiments of the present disclosure generally relate to a semiconductor device including layers of group III-V semiconductor materials. In one embodiment, the semiconductor device includes a phosphorous containing layer deposited on a silicon substrate, wherein a lattice mismatch between the phosphorous containing layer and the silicon substrate is less than 5%, a group III-V compound nucleation layer deposited on the phosphorous containing layer at a first temperature, the group III-V compound nucleation layer having a first thickness, a group III-V compound transition layer deposited on the group III-V compound nucleation layer at a second temperature higher than the first temperature, the group III-V compound transition layer having a second thickness larger than the first thickness, and the group III-V compound nucleation layer is different from the group III-V compound transition layer, and an active layer deposited on the group III-V compound transition layer.

Abstract: Embodiments of the present disclosure generally relate to a film stack including layers of group III-V semiconductor materials. The film stack includes a phosphorous containing layer deposited over a silicon substrate, a GaAs containing layer deposited on the phosphorous containing layer, and an aluminum containing layer deposited on the GaAs containing layer. The GaAs containing layer between the phosphorous containing layer and the aluminum containing layer improves the surface smoothness of the aluminum containing layer.