Abstract: A semiconductor package including a first semiconductor chip including a logic structure and a second semiconductor chip bonded to the first semiconductor chip may be provided. The first semiconductor chip may include signal lines on a first surface of a first semiconductor substrate and connected to the logic structure, a power delivery network on a second surface of the first semiconductor substrate, the second surface being opposite to the first surface, and penetration vias penetrating the first semiconductor substrate and connecting the power delivery network to the logic structure. The second semiconductor chip may include a capacitor layer that is on a second semiconductor substrate and is adjacent to the power delivery network.

Abstract: An electronic device with embedded access to a high-bandwidth, high-capacity fast-access memory includes (a) a memory circuit fabricated on a first semiconductor die, wherein the memory circuit includes numerous modular memory units, each modular memory unit having (i) a three-dimensional array of storage transistors, and (ii) a group of conductors exposed to a surface of the first semiconductor die, the group of conductors being configured for communicating control, address and data signals associated the memory unit; and (b) a logic circuit fabricated on a second semiconductor die, wherein the logic circuit also includes conductors each exposed at a surface of the second semiconductor die, wherein the first and second semiconductor dies are wafer-bonded, such that the conductors exposed at the surface of the first semiconductor die are each electrically connected to a corresponding one of the conductors exposed to the surface of the second semiconductor die.

Abstract: A memory system includes: (a) a memory array including numerous quasi-volatile (“QV”) memory units each configured to store a first portion of a code word encoded using an error-detecting and error-correcting code (“ECC-encoded code word”); (b) a refresh circuit for reading and writing back the first portion of the ECC-encoded code word of a selected one of the QV memory unit; (c) a global parity evaluation circuit configured to determine a global parity of the ECC-encoded code word of the selected QV memory unit; and a memory controller configured for controlling operations carried out in the memory array, wherein when the global parity of the ECC-encoded code word of the selected QV memory unit is determined at the global parity evaluation circuit to be a predetermined parity, the memory controller (i) performs error correction on the selected ECC-encoded code word and (ii) causes the first portion of the corrected ECC-encoded code word to be written back to the selected QV memory unit, instead of the refre

Abstract: A teleoperated material handling system 100 includes a teleoperation terminal 10 for collecting mechanical inputs from a teleoperator and converting to operation commands, a material handling vehicle 20 with a load engaging device 21, a visual capturing module 22 for capturing video imagery in front of the material handling vehicle, a communication module 30 for establishing a communication link with the teleoperation terminal for transmitting the video imagery to the teleoperation terminal and receiving the operation commands, and a control module 40 for controlling operations of the material handling vehicle and the load engaging device. The system further includes an assistive module 50 providing an assistive indicator to the teleoperator through the teleoperation terminal, the assistive indicator 51 is dynamic with respect to changes in the operation commands, and provides visual guidance for the teleoperator in maneuvering the load engaging device.

Abstract: An electronic device with embedded access to a high-bandwidth, high-capacity fast-access memory includes (a) a memory circuit fabricated on a first semiconductor die, wherein the memory circuit includes numerous modular memory units, each modular memory unit having (i) a three-dimensional array of storage transistors, and (ii) a group of conductors exposed to a surface of the first semiconductor die, the group of conductors being configured for communicating control, address and data signals associated the memory unit; and (b) a logic circuit fabricated on a second semiconductor die, wherein the logic circuit also includes conductors each exposed at a surface of the second semiconductor die, wherein the first and second semiconductor dies are wafer-bonded, such that the conductors exposed at the surface of the first semiconductor die are each electrically connected to a corresponding one of the conductors exposed to the surface of the second semiconductor die.

Abstract: A method of controlling a guide machine and a navigation system. The navigation system includes: a plurality of signal sources deployed in a predetermined area; a guide machine including a signal receiver arranged to receive electromagnetic signals emitted from one or more of the plurality of signal sources; and a processor arranged to process the electromagnetic signals to identify the locations of the signal sources, and thereby to determine a current position of the guide machine with reference to the locations of the signal sources; and the processor is further arranged to determine a path for the guide machine to travel from the current position to a destination location in the predetermined area.

Abstract: An electronic device with embedded access to a high-bandwidth, high-capacity fast-access memory includes (a) a memory circuit fabricated on a first semiconductor die, wherein the memory circuit includes numerous modular memory units, each modular memory unit having (i) a three-dimensional array of storage transistors, and (ii) a group of conductors exposed to a surface of the first semiconductor die, the group of conductors being configured for communicating control, address and data signals associated the memory unit; and (b) a logic circuit fabricated on a second semiconductor die, wherein the logic circuit also includes conductors each exposed at a surface of the second semiconductor die, wherein the first and second semiconductor dies are wafer-bonded, such that the conductors exposed at the surface of the first semiconductor die are each electrically connected to a corresponding one of the conductors exposed to the surface of the second semiconductor die.

Abstract: A high-capacity system memory may be built from both quasi-volatile (QV) memory circuits, logic circuits, and static random-access memory (SRAM) circuits. Using the SRAM circuits as buffers or cache for the QV memory circuits, the system memory may achieve access latency performance of the SRAM circuits and may be used as code memory. The system memory is also capable of direct memory access (DMA) operations and includes an arithmetic logic unit for performing computational memory tasks. The system memory may include one or more embedded processor. In addition, the system memory may be configured for multi-channel memory accesses by multiple host processors over multiple host ports. The system memory may be provided in the dual-in-line memory module (DIMM) format.

Abstract: An ultra-wideband-based system and method for detecting properties associated with a movable object in an environment such as an indoor environment. The method includes transmitting ultra-wideband radar signals to an environment, using an ultra-wideband transmitter, and receiving signals reflected from the environment as a result of the transmission of the first ultra-wideband radar signals using an ultra-wideband receiver. The method also includes processing the reflected signals and determining properties associated with a movable object in an environment based on the processed reflected signals, using the processor.

Abstract: A high-capacity system memory may be built from both quasi-volatile (QV) memory circuits, logic circuits, and static random-access memory (SRAM) circuits. Using the SRAM circuits as buffers or cache for the QV memory circuits, the system memory may achieve access latency performance of the SRAM circuits and may be used as code memory. The system memory is also capable of direct memory access (DMA) operations and includes an arithmetic logic unit for performing computational memory tasks. The system memory may include one or more embedded processor. In addition, the system memory may be configured for multi-channel memory accesses by multiple host processors over multiple host ports. The system memory may be provided in the dual-in-line memory module (DIMM) format.

Abstract: An ultra-wideband-based object identification method and system includes: transmitting, using a transmitter, an ultra wideband signal to an object; receiving, using a receiver, a reflected signal from the object; and determining, using a processor, an identity of the object based on the received reflected signal.

Abstract: Virtual 3D display apparatus has a display zone, an optical fiber assembly and a motor. The optical fiber assembly includes optical fibers each having an input end for entrance of light and an output end. There are light sources each at the input end of a respective optical fiber for generating a light signal that enters and travels along the optical fiber and is then emitted at the output end thereof. The emitted light signals together form a virtual 3D image in the display zone upon rotation of the optical fiber assembly by the motor. There are also control elements at the input ends of respective optical fibers, each for operation to make adjustment of the virtual 3D image based on a control signal that travels along the respective optical fiber, with the adjustment to be made to a part of the virtual 3D image associated with the same optical fiber.

Abstract: A memory system includes: (a) a memory array including numerous quasi-volatile (“QV”) memory units each configured to store a first portion of a code word encoded using an error-detecting and error-correcting code (“ECC-encoded code word”); (b) a refresh circuit for reading and writing back the first portion of the ECC-encoded code word of a selected one of the QV memory unit; (c) a global parity evaluation circuit configured to determine a global parity of the ECC-encoded code word of the selected QV memory unit; and a memory controller configured for controlling operations carried out in the memory array, wherein when the global parity of the ECC-encoded code word of the selected QV memory unit is determined at the global parity evaluation circuit to be a predetermined parity, the memory controller (i) performs error correction on the selected ECC-encoded code word and (ii) causes the first portion of the corrected ECC-encoded code word to be written back to the selected QV memory unit, instead of the refre

Abstract: An electronic device with embedded access to a high-bandwidth, high-capacity fast-access memory includes (a) a memory circuit fabricated on a first semiconductor die, wherein the memory circuit includes numerous modular memory units, each modular memory unit having (i) a three-dimensional array of storage transistors, and (ii) a group of conductors exposed to a surface of the first semiconductor die, the group of conductors being configured for communicating control, address and data signals associated the memory unit; and (b) a logic circuit fabricated on a second semiconductor die, wherein the logic circuit also includes conductors each exposed at a surface of the second semiconductor die, wherein the first and second semiconductor dies are wafer-bonded, such that the conductors exposed at the surface of the first semiconductor die are each electrically connected to a corresponding one of the conductors exposed to the surface of the second semiconductor die.

Abstract: A method of controlling a guide machine and a navigation system. The navigation system includes: a plurality of signal sources deployed in a predetermined area; a guide machine including a signal receiver arranged to receive electromagnetic signals emitted from one or more of the plurality of signal sources; and a processor arranged to process the electromagnetic signals to identify the locations of the signal sources, and thereby to determine a current position of the guide machine with reference to the locations of the signal sources; and the processor is further arranged to determine a path for the guide machine to travel from the current position to a destination location in the predetermined area.

Abstract: A high-capacity system memory may be built from both quasi-volatile (QV) memory circuits, logic circuits, and static random-access memory (SRAM) circuits. Using the SRAM circuits as buffers or cache for the QV memory circuits, the system memory may achieve access latency performance of the SRAM circuits and may be used as code memory. The system memory is also capable of direct memory access (DMA) operations and includes an arithmetic logic unit for performing computational memory tasks. The system memory may include one or more embedded processor. In addition, the system memory may be configured for multi-channel memory accesses by multiple host processors over multiple host ports. The system memory may be provided in the dual-in-line memory module (DIMM) format.

Abstract: A chatbot server that manages context information between a chatbot and a user device includes a receiving unit that receives, from a messenger server, a question message input for a service selected from multiple services by the user device and service account information corresponding to the selected service; a derivation unit that derives an answer to the question message by using the chatbot corresponding to the service account information; and a context information management unit that manages context information of a chat between the user device and the chatbot based on the question message and/or the answer.

Abstract: An ultra-wideband-based system and method for detecting properties associated with a movable object in an environment such as an indoor environment. The method includes transmitting ultra-wideband radar signals to an environment, using an ultra-wideband transmitter, and receiving signals reflected from the environment as a result of the transmission of the first ultra-wideband radar signals using an ultra-wideband receiver. The method also includes processing the reflected signals and determining properties associated with a movable object in an environment based on the processed reflected signals, using the processor.

Abstract: An electronic device with embedded access to a high-bandwidth, high-capacity fast-access memory includes (a) a memory circuit fabricated on a first semiconductor die, wherein the memory circuit includes numerous modular memory units, each modular memory unit having (i) a three-dimensional array of storage transistors, and (ii) a group of conductors exposed to a surface of the first semiconductor die, the group of conductors being configured for communicating control, address and data signals associated the memory unit; and (b) a logic circuit fabricated on a second semiconductor die, wherein the logic circuit also includes conductors each exposed at a surface of the second semiconductor die, wherein the first and second semiconductor dies are wafer-bonded, such that the conductors exposed at the surface of the first semiconductor die are each electrically connected to a corresponding one of the conductors exposed to the surface of the second semiconductor die.