Patents by Inventor Keungjin Sohn
Keungjin Sohn has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8997340Abstract: A method of manufacturing an insulating sheet, the method including providing a reinforcement material having a thermoplastic resin layer stacked thereon; stacking the thermoplastic resin layer stacked on the reinforcement material over a core substrate; and hot pressing the reinforcement material and the thermoplastic resin layer onto the core substrate.Type: GrantFiled: September 21, 2011Date of Patent: April 7, 2015Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Keungjin Sohn, Nobuyuki Ikeguchi, Joung-Gul Ryu, Ho-Sik Park, Sang-Youp Lee, Joon-Sik Shin, Jung-Hwan Park
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Patent number: 8647926Abstract: A method of fabricating a semiconductor plastic package can include: providing a core board, which includes at least one pad, and which has a coefficient of thermal expansion of 9 ppm/° C. or lower; stacking a build-up insulation layer over the core board; forming an opening by removing a portion of the build-up insulation layer such that the pad is exposed to the exterior; and placing a semiconductor chip in the opening and electrically connecting the semiconductor chip with the pad. This method can be utilized to provide higher reliability in the connection between the semiconductor chip and the circuit board.Type: GrantFiled: August 31, 2010Date of Patent: February 11, 2014Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Joon-Sik Shin, Nobuyuki Ikeguchi, Keungjin Sohn, Joung Gul Ryu, Sang-Youp Lee, Jung-Hwan Park, Ho-Sik Park
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Patent number: 8499441Abstract: A method of manufacturing a printed circuit board includes stacking a solder resist layer on one side of a carrier; forming a first circuit pattern, which includes a first electrode pad, on the solder resist layer; forming a conductive post on the first electrode pad; stacking and pressing the carrier onto an insulation layer stacked in an inner substrate, such that the conductive post faces the insulation layer; and removing the carrier. As the conductive posts are pressed into the insulation layers to implement interlayer connections, certain drilling processes for forming via holes may be omitted, so that the degree of freedom can be increased in designing the circuits, and the circuits can be made to have greater densities. As the circuit patterns are buried in the insulation layers, the board can be made thinner, and the attachment areas can be increased, to allow greater adhesion.Type: GrantFiled: January 28, 2008Date of Patent: August 6, 2013Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Jung-Hwan Park, Keungjin Sohn, Joon-Sik Shin, Sang-Youp Lee, Ho-Sik Park, Joung-Gul Ryu
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Publication number: 20120174393Abstract: A method of fabricating a multilayered printed circuit board, the method including: providing a core substrate having an outer circuit, the core substrate having a thermal expansion coefficient of 10 to 20 ppm/° C. at ?60 to 150° C.; stacking a stress-relieving insulation layer on either side of the core substrate, the stress-relieving insulation layer having a thermal expansion coefficient of ?20 to 6 ppm/° C.; and forming a metal layer on the insulation layer and forming at least one pad by removing at least one portion of the metal layer and electrically connecting the pad with the outer circuit.Type: ApplicationFiled: March 21, 2012Publication date: July 12, 2012Applicant: Samsung Electro-Mechanics Co., Ltd.Inventors: Nobuyuki IKEGUCHI, Keungjin Sohn, Joon-Sik Shin
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Patent number: 8174128Abstract: A method of manufacturing a semiconductor package that includes: forming a first board; forming second boards, in each of which at least one cavity is formed; attaching the second boards to both sides of the first board, such that the second boards are electrically connected with the first board; and connecting at least one component with the first board by a flip chip method by embedding the component in the cavity. The method can prevent damage to the semiconductor chips and lower manufacturing costs, while the connection material may also mitigate stresses, to prevent cracking in the boards and semiconductor chips, while preventing defects such as bending and warpage. Defects caused by temperature changes may also be avoided. Furthermore, it is not necessary to use an underfill in the portions where the semiconductor chips are connected with the printed circuit board, which allows for easier reworking and lower costs.Type: GrantFiled: July 22, 2010Date of Patent: May 8, 2012Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Nobuyuki Ikeguchi, Keungjin Sohn, JoonSik Shin, Jung-Hwan Park
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Publication number: 20120012247Abstract: A method of manufacturing an insulating sheet, the method including providing a reinforcement material having a thermoplastic resin layer stacked thereon; stacking the thermoplastic resin layer stacked on the reinforcement material over a core substrate; and hot pressing the reinforcement material and the thermoplastic resin layer onto the core substrate.Type: ApplicationFiled: September 21, 2011Publication date: January 19, 2012Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Keungjin Sohn, Nobuyuki Ikeguchi, Joung-Gul Ryu, Ho-Sik Park, Sang-Youp Lee, Joon-Sik Shin, Jung-Hwan Park
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Patent number: 8030752Abstract: A method of manufacturing a semiconductor package may include: forming a first board; forming second boards, in each of which at least one cavity is formed; attaching the second boards to both sides of the first board, such that the second boards are electrically connected with the first board; and connecting at least one component with the first board by a flip chip method by embedding the component in the cavity. The method can prevent damage to the semiconductor chips and lower manufacturing costs, while the connection material may also mitigate stresses, to prevent cracking in the boards and semiconductor chips, while preventing defects such as bending and warpage. Defects caused by temperature changes may also be avoided. Furthermore, it is not necessary to use an underfill in the portions where the semiconductor chips are connected with the printed circuit board, which allows for easier reworking and lower costs.Type: GrantFiled: June 24, 2008Date of Patent: October 4, 2011Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Nobuyuki Ikeguchi, Keungjin Sohn, JoonSik Shin, Jung-Hwan Park
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Publication number: 20110139499Abstract: A printed circuit board the includes: an insulation layer; a first circuit pattern including a first electrode pad buried in the insulation layer such that a portion of the first circuit pattern is exposed at a surface of the insulation layer; an inner substrate having the insulation layer stacked therein and having a second circuit pattern including a second electrode pad formed thereon; a conductive post buried in the insulation layer such that one end thereof is connected to the first electrode pad and the other end thereof is connected to the second electrode pad; and a solder resist layer stacked on the insulation layer.Type: ApplicationFiled: February 18, 2011Publication date: June 16, 2011Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Jung-Hwan Park, Keungjin Sohn, Joon-Sik Shin, Sang-Youp Lee, Ho-Sik Park, Joung-Gul Ryu
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Patent number: 7893527Abstract: A semiconductor plastic package and a method of fabricating the semiconductor plastic package are disclosed. A method of fabricating a semiconductor plastic package can include: providing a core board, which includes at least one pad, and which has a coefficient of thermal expansion of 9 ppm/° C. or lower; stacking a build-up insulation layer over the core board; forming an opening by removing a portion of the build-up insulation layer such that the pad is exposed to the exterior; and placing a semiconductor chip in the opening and electrically connecting the semiconductor chip with the pad. This method can be utilized to provide higher reliability in the connection between the semiconductor chip and the circuit board.Type: GrantFiled: July 2, 2008Date of Patent: February 22, 2011Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Joon-Sik Shin, Nobuyuki Ikeguchi, Keungjin Sohn, Joung-Gul Ryu, Sang-Youp Lee, Jung-Hwan Park, Ho-Sik Park
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Publication number: 20100330747Abstract: A method of fabricating a semiconductor plastic package can include: providing a core board, which includes at least one pad, and which has a coefficient of thermal expansion of 9 ppm/° C. or lower; stacking a build-up insulation layer over the core board; forming an opening by removing a portion of the build-up insulation layer such that the pad is exposed to the exterior; and placing a semiconductor chip in the opening and electrically connecting the semiconductor chip with the pad. This method can be utilized to provide higher reliability in the connection between the semiconductor chip and the circuit board.Type: ApplicationFiled: August 31, 2010Publication date: December 30, 2010Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Joon-Sik Shin, Nobuyuki Ikeguchi, Keungjin Sohn, Joung-Gul Ryu, Sang-Youp Lee, Jung-Hwan Park, Ho-Sik Park
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Publication number: 20100291737Abstract: A method of manufacturing a semiconductor package that includes: forming a first board; forming second boards, in each of which at least one cavity is formed; attaching the second boards to both sides of the first board, such that the second boards are electrically connected with the first board; and connecting at least one component with the first board by a flip chip method by embedding the component in the cavity. The method can prevent damage to the semiconductor chips and lower manufacturing costs, while the connection material may also mitigate stresses, to prevent cracking in the boards and semiconductor chips, while preventing defects such as bending and warpage. Defects caused by temperature changes may also be avoided. Furthermore, it is not necessary to use an underfill in the portions where the semiconductor chips are connected with the printed circuit board, which allows for easier reworking and lower costs.Type: ApplicationFiled: July 22, 2010Publication date: November 18, 2010Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Nobuyuki Ikeguchi, Keungjin Sohn, JoonSik Shin, Jung-Hwan Park
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Publication number: 20090242248Abstract: A method of manufacturing an insulating sheet can include: providing a reinforcement material on which a thermoplastic resin layer is stacked, stacking the thermoplastic resin layer stacked on the reinforcement material over a core substrate, and hot pressing the reinforcement material and the thermoplastic resin layer onto the core substrate. This method can be used to produce an insulation board that has a coefficient of thermal expansion close to that of the semiconductor chip, and thereby prevent bending or warpage in the printed circuit board using the insulation board. Furthermore, the stress in the connecting material can be reduced, so that cracking or delamination in the connecting material may be avoided, while heat-releasing performance may also be improved.Type: ApplicationFiled: December 23, 2008Publication date: October 1, 2009Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Keungjin Sohn, Nobuyuki Ikeguchi, Joung-Gul Ryu, Ho-Sik Park, Sang-Youp Lee, Joon-Sik Shin, Jung-Hwan Park
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Publication number: 20090236038Abstract: A method for manufacturing an insulating sheet, a method for manufacturing a metal clad laminate, and a method for manufacturing a printed circuit board are disclosed. The method for manufacturing an insulating sheet may include stacking a thermoplastic resin layer over a reinforcement material, and hot pressing the thermoplastic resin layer into the reinforcement material to impregnate and attach the thermoplastic resin layer into the reinforcement material. Certain embodiments of the invention can be utilized to produce an insulation board that has a coefficient of thermal expansion close to that of the semiconductor chip, and thereby prevent bending or warpage in the multi-layer printed circuit board using the insulation board. Furthermore, the stress in the material connecting the semiconductor chip with the printed circuit board can be reduced, so that cracking or delamination in the connecting material, such as lead-free solder, may be avoided.Type: ApplicationFiled: August 20, 2008Publication date: September 24, 2009Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTDInventors: Nobuyuki Ikeguchi, Keungjin Sohn, Joon-Sik Shin, Joung-Gul Ryu, Jung-Hwan Park, Ho-Sik Park
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Publication number: 20090152742Abstract: A method of manufacturing a semiconductor package may include: forming a first board; forming second boards, in each of which at least one cavity is formed; attaching the second boards to both sides of the first board, such that the second boards are electrically connected with the first board; and connecting at least one component with the first board by a flip chip method by embedding the component in the cavity. The method can prevent damage to the semiconductor chips and lower manufacturing costs, while the connection material may also mitigate stresses, to prevent cracking in the boards and semiconductor chips, while preventing defects such as bending and warpage. Defects caused by temperature changes may also be avoided. Furthermore, it is not necessary to use an underfill in the portions where the semiconductor chips are connected with the printed circuit board, which allows for easier reworking and lower costs.Type: ApplicationFiled: June 24, 2008Publication date: June 18, 2009Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Nobuyuki Ikeguchi, Keungjin Sohn, JoonSik Shin, Jung-Hwan Park
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Publication number: 20090084595Abstract: A method of manufacturing a printed circuit board includes stacking a solder resist layer on one side of a carrier; forming a first circuit pattern, which includes a first electrode pad, on the solder resist layer; forming a conductive post on the first electrode pad; stacking and pressing the carrier onto an insulation layer stacked in an inner substrate, such that the conductive post faces the insulation layer; and removing the carrier. As the conductive posts are pressed into the insulation layers to implement interlayer connections, certain drilling processes for forming via holes may be omitted, so that the degree of freedom can be increased in designing the circuits, and the circuits can be made to have greater densities. As the circuit patterns are buried in the insulation layers, the board can be made thinner, and the attachment areas can be increased, to allow greater adhesion.Type: ApplicationFiled: January 28, 2008Publication date: April 2, 2009Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Jung-Hwan Park, Keungjin Sohn, Joon-Sik Shin, Sang-Youp Lee, Ho-Sik Park, Joung-Gul Ryu
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Publication number: 20090026604Abstract: A semiconductor plastic package and a method of fabricating the semiconductor plastic package are disclosed. A method of fabricating a semiconductor plastic package can include: providing a core board, which includes at least one pad, and which has a coefficient of thermal expansion of 9 ppm/° C. or lower; stacking a build-up insulation layer over the core board; forming an opening by removing a portion of the build-up insulation layer such that the pad is exposed to the exterior; and placing a semiconductor chip in the opening and electrically connecting the semiconductor chip with the pad. This method can be utilized to provide higher reliability in the connection between the semiconductor chip and the circuit board.Type: ApplicationFiled: July 2, 2008Publication date: January 29, 2009Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Joon-Sik Shin, Nobuyuki Ikeguchi, Keungjin Sohn, Joung-Gul Ryu, Sang-Youp Lee, Jung-Hwan Park, Ho-Sik Park
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Publication number: 20090008136Abstract: A multilayered printed circuit board and a method of fabricating the printed circuit board are disclosed. The method of fabricating the multilayered printed circuit board can include: providing a core substrate, which has an outer circuit, and which has a thermal expansion coefficient of 10 to 20 ppm/° C. at ?60 to 150° C.; stacking a stress-relieving insulation layer, which has a thermal expansion coefficient of ?20 to 6 ppm/° C., on either side of the core substrate; and forming a metal layer on the insulation layer and forming at least one pad and electrically connecting the pad with the outer circuit. This method can provide high reliability, as the stress-relieving insulation layers can prevent bending and warpage, etc., in the board overall.Type: ApplicationFiled: June 25, 2008Publication date: January 8, 2009Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Nobuyuki Ikeguchi, Keungjin Sohn, Joon-Sik Shin