Abstract: A display device includes a substrate having a light emitting area and a non-light emitting area; a first anode electrode on the light emitting area of the substrate; a pixel defining layer on the non-light emitting area of the substrate and defining a first opening; an organic separator layer on the pixel defining layer and defining a second opening; a first light emitting layer on the first anode electrode; a common electron layer on the first light emitting layer and the organic separator layer; and a common electrode on the common electron layer, wherein the organic separator layer does not overlap the light emitting area, and overlaps the non-light emitting area to be in contact with the pixel defining layer, the first light emitting layer, and the common electron layer.

Abstract: A semiconductor package including a package substrate including a mounting region and at least one through-hole arranged in the mounting region, and a semiconductor chip mounted on the mounting region, the semiconductor chip including a first side and a second side, the second side of the semiconductor chip being opposite to the first side of the semiconductor chip, the at least one through-hole of the package substrate being closer to the second side of the semiconductor chip than the first side of the semiconductor chip may be provided.

Abstract: A semiconductor package includes a package substrate including at least one through-hole in a chip mounting region, a plurality of wiring patterns at a top surface of the package substrate. The wiring patterns include respective extension portions and respective landing pads. At least some of the landing pads obliquely extend toward the through-hole. Conductive bumps are formed on corresponding landing pads to connect to a semiconductor chip mounted on the chip mounting region of the package substrate. A molding material extends between the top surface of the package substrate and the semiconductor chip and fills the through-hole.

Abstract: A semiconductor package including a package substrate including a mounting region and at least one through-hole arranged in the mounting region, and a semiconductor chip mounted on the mounting region, the semiconductor chip including a first side and a second side, the second side of the semiconductor chip being opposite to the first side of the semiconductor chip, the at least one through-hole of the package substrate being closer to the second side of the semiconductor chip than the first side of the semiconductor chip may be provided.

Abstract: A semiconductor package includes a package substrate including at least one through-hole in a chip mounting region, a plurality of wiring patterns at a top surface of the package substrate. The wiring patterns include respective extension portions and respective landing pads. At least some of the landing pads obliquely extend toward the through-hole. Conductive bumps are formed on corresponding landing pads to connect to a semiconductor chip mounted on the chip mounting region of the package substrate. A molding material extends between the top surface of the package substrate and the semiconductor chip and fills the through-hole.

Abstract: A semiconductor package includes a package substrate including at least one through-hole in a chip mounting region, a plurality of wiring patterns at a top surface of the package substrate. The wiring patterns include respective extension portions and respective landing pads. At least some of the landing pads obliquely extend toward the through-hole. Conductive bumps are formed on corresponding landing pads to connect to a semiconductor chip mounted on the chip mounting region of the package substrate. A molding material extends between the top surface of the package substrate and the semiconductor chip and fills the through-hole.

Abstract: A semiconductor package includes a package substrate including at least one through-hole in a chip mounting region, a plurality of wiring patterns at a top surface of the package substrate. The wiring patterns include respective extension portions and respective landing pads. At least some of the landing pads obliquely extend toward the through-hole. Conductive bumps are formed on corresponding landing pads to connect to a semiconductor chip mounted on the chip mounting region of the package substrate. A molding material extends between the top surface of the package substrate and the semiconductor chip and fills the through-hole.

Abstract: The method of transmitting data in real time with low power via a wireless line in which channel status is searched to prevent data loss by transmitting and receiving retransmission a packet every time when there is an interference, and to minimize power consumption necessary for transmission and reception by transmitting and receiving the retransmission packet at a specific period when there is no interference. The method includes: transmitting real time packet data containing reply requesting information from a master to a slave; determining channel status by analyzing whether the master receives the reply packet and reply information; and adjusting the number of times of requesting the reply packet by selectively recording the reply requesting information contained in a control information field of the real time packet data according to the determined channel status. Power consumption due to the transmission and reception of the reply packet can then be reduced.

Abstract: A method for manufacturing a thin film transistor having a more uniform threshold voltage, and a flat panel display device that includes the thin film transistor. The method includes forming an amorphous silicon film on a substrate, removing a silicon oxide layer from a surface of the amorphous silicon film, forming a silicon oxide layer on the surface of the amorphous silicon film, and forming a polycrystalline Si layer by crystallizing the amorphous silicon film.

Abstract: An apparatus and method for inspecting polycrystalline silicon (Poly-Si) that illuminates light onto protrusions in the Poly-Si in order to determine a distance between them using intensity and reflection angle of reflected light. The Poly-Si inspection apparatus includes a light source that illuminates light, and a reflected light detector for receiving reflected light, wherein a distance between protrusions is measured by an incident angle of the light illuminated into the protrusion from the light source, a detection angle of the reflected light detector, and a wavelength of the detected reflected light.

Abstract: The invention relates to a real-time data transmission method, and more particularly to a real-time data transmission method using a Frequency Hopping Spread Spectrum (FHSS) in which a frequency channel, which causes no interference in real-time data transmission, is found to transmit data. In this method, when data is transmitted in real time through a setting channel, a channel in good state is acquired after a setting time through comparison with a test channel and, to prepare for interference that may occur during data transmission, the setting channel is previously changed to another channel before interference occurs, so that real-time data is transmitted while maintaining the continuity of data transmission, thereby minimizing data loss.

Abstract: A short distance wireless data transmission system and method which are capable of minimizing data loss are disclosed. The short distance wireless data transmission system can monitor variation amount of memory data, which is buffered in the master side when data transmission errors occur, can perform re-transmission of data having transmission errors, and can perform a change toward new replacement channel without interference if variation amount of memory data, which is buffered therein, exceeds a predetermined reference value to re-transmit from data in which the first transmission error occurs thereto, such that real time data cannot be lost, although a channel change is generated by successive channel interference.

Abstract: A method for manufacturing a thin film transistor having a more uniform threshold voltage, and a flat panel display device that includes the thin film transistor. The method includes forming an amorphous silicon film on a substrate, removing a silicon oxide layer from a surface of the amorphous silicon film, forming a silicon oxide layer on the surface of the amorphous silicon film, and forming a polycrystalline Si layer by crystallizing the amorphous silicon film.

Abstract: An apparatus and method for inspecting polycrystalline silicon (Poly-Si) that illuminates light onto protrusions in the Poly-Si in order to determine a distance between them using intensity and reflection angle of reflected light. The Poly-Si inspection apparatus includes a light source that illuminates light, and a reflected light detector for receiving reflected light, wherein a distance between protrusions is measured by an incident angle of the light illuminated into the protrusion from the light source, a detection angle of the reflected light detector, and a wavelength of the detected reflected light.

Abstract: A method of manufacturing a CMOS thin film transistor (TFT) active matrix organic EL device using six mask processes. The manufacturing methods is simpler than previous manufacturing methods, resulting in high manufacturing yield and low production cost.

Abstract: A method of manufacturing a CMOS thin film transistor (TFT) active matrix organic EL device using six mask processes. The manufacturing methods is simpler than previous manufacturing methods, resulting in high manufacturing yield and low production cost.

Abstract: In order to execute a rapid and effective DCT and IDCT and embody DCT and IDCT in one processor, in an inventive DCT/IDCT processor, an input multiplexer selects DCT or IDCT coefficients and transfers the coefficients to a matrix multiplier, and DCT/IDCT deciding unit within the matrix multiplier controls a flow of the DCT and IDCT coefficients. An output multiplexer decides an output of the DCT and the IDCT, to thereby embody the DCT and the IDCT in one processor, and perform the DCT and the IDCT at a high speed by reducing the number of multiplication calculation, namely through a decrease of the calculation number.

Abstract: A field effect transistor includes laterally spaced apart source and drain regions in a substrate, laterally spaced apart undoped regions in the substrate between the laterally spaced apart source and drain regions, a doped channel region in the substrate between the laterally spaced apart undoped regions, and a gate insulating layer on the substrate. A main gate is on the gate insulating layer opposite the channel, and first and second sub gates are on the gate insulating layer, a respective one of which is opposite a respective one of the spaced apart undoped regions. The first and second sub gates are laterally spaced apart from and electrically insulated from the main gate.

Abstract: A field effect transistor includes laterally spaced apart source and drain regions in a substrate, laterally spaced apart undoped regions in the substrate between the laterally spaced apart source and drain regions, a doped channel region in the substrate between the laterally spaced apart undoped regions, and a gate insulating layer on the substrate. A main gate is on the gate insulating layer opposite the channel, and first and second sub gates are on the gate insulating layer, a respective one of which is opposite a respective one of the spaced apart undoped regions. The first and second sub gates are laterally spaced apart from and electrically insulated from the main gate.

Abstract: A field effect transistor includes laterally spaced apart source and drain regions in a substrate, laterally spaced apart undoped regions in the substrate between the laterally spaced apart source and drain regions, a doped channel region in the substrate between the laterally spaced apart undoped regions, and a gate insulating layer on the substrate. A main gate is on the gate insulating layer opposite the channel, and first and second sub gates are on the gate insulating layer, a respective one of which is opposite a respective one of the spaced apart undoped regions. The first and second sub gates are laterally spaced apart from and electrically insulated from the main gate.