Patents by Inventor Keunsoo ROH

Keunsoo ROH has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9754655
    Abstract: In an embodiment, a dynamic random-access memory (DRAM) system configures an inactive portion of a DRAM die to operate in accordance with a self-refresh mode that is characterized by refreshes of the DRAM die being controlled by a local DRAM die controller integrated into the DRAM die. The DRAM system also configures an active portion of the DRAM die to operate in accordance with a controller-managed refresh mode while the inactive portion of the DRAM die operates in the self-refresh mode, the controller-managed refresh mode characterized by refreshes of the DRAM die being controlled by a controller that is external to the DRAM die.
    Type: Grant
    Filed: November 1, 2016
    Date of Patent: September 5, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Mosaddiq Saifuddin, SankaraRao Kunapareddy, Keunsoo Roh, Chun Xiang He, Pratik Patel, Nicholas Ambur, Jeremy Haugen
  • Patent number: 9690364
    Abstract: Systems, methods, and computer programs are disclosed for dynamically adjusting memory power state transition timers. One embodiment of a method comprises receiving one or more parameters impacting usage or performance of a memory device coupled to a processor in a computing device. An optimal value is determined for one or more memory power state transition timer settings. A current value is updated for the memory power state transition timer settings with the optimal value.
    Type: Grant
    Filed: September 4, 2015
    Date of Patent: June 27, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Hee Jun Park, Haw-Jing Lo, Keunsoo Roh
  • Publication number: 20170148504
    Abstract: In an embodiment, a dynamic random-access memory (DRAM) system configures an inactive portion of a DRAM die to operate in accordance with a self-refresh mode that is characterized by refreshes of the DRAM die being controlled by a local DRAM die controller integrated into the DRAM die. The DRAM system also configures an active portion of the DRAM die to operate in accordance with a controller-managed refresh mode while the inactive portion of the DRAM die operates in the self-refresh mode, the controller-managed refresh mode characterized by refreshes of the DRAM die being controlled by a controller that is external to the DRAM die.
    Type: Application
    Filed: November 1, 2016
    Publication date: May 25, 2017
    Inventors: Mosaddiq SAIFUDDIN, SankaraRao KUNAPAREDDY, Keunsoo ROH, Chun Xiang HE, Pratik PATEL, Nicholas AMBUR, Jeremy HAUGEN
  • Publication number: 20170068308
    Abstract: Systems, methods, and computer programs are disclosed for dynamically adjusting memory power state transition timers. One embodiment of a method comprises receiving one or more parameters impacting usage or performance of a memory device coupled to a processor in a computing device. An optimal value is determined for one or more memory power state transition timer settings. A current value is updated for the memory power state transition timer settings with the optimal value.
    Type: Application
    Filed: September 4, 2015
    Publication date: March 9, 2017
    Inventors: HEE JUN PARK, Haw-Jing LO, Keunsoo ROH