Abstract: Disclosed is an analog-to-digital converter (ADC) circuit for digitizing a pixel signal into a digital signal of positive integer (N) bits. The ADC includes a ramp generator, a clock, a comparator, and a counter. A system clock signal allows the ramp generator to generate a ramp signal and the clock generator to generate first to N-th clock signals. The comparator generates a comparison signal based on a comparison of the pixel signal, received from a pixel array, and the ramp signal. The counter includes an additional latch circuit and first to N-th latch circuits. The additional latch circuit generates an additional binary signal based on the system clock signal and the comparison signal, and the first to N-th latch circuits generate first to N-th latch signals based on the comparison signal and corresponding clock signal.

Abstract: Disclosed is an analog-to-digital converter including a comparison circuit and a counter circuit. The comparison circuit outputs a comparison result signal based on a pixel signal and a ramp signal and outputs a zero-crossing prediction signal, is the comparison circuit being configured to transition the zero-crossing prediction signal before a zero-crossing time point at which a voltage level of the pixel signal becomes identical to a voltage level of the ramp signal and during a time interval during which the voltage level of the ramp signal is reduced. The counter circuit outputs a low-order bit digital code based on the zero-crossing prediction signal and stops the output of the low-order bit digital code based on the comparison result signal.

Abstract: Disclosed is an analog-to-digital converter including a comparison circuit and a counter circuit. The comparison circuit outputs a comparison result signal based on a pixel signal and a ramp signal and outputs a zero-crossing prediction signal, is the comparison circuit being configured to transition the zero-crossing prediction signal before a zero-crossing time point at which a voltage level of the pixel signal becomes identical to a voltage level of the ramp signal and during a time interval during which the voltage level of the ramp signal is reduced. The counter circuit outputs a low-order bit digital code based on the zero-crossing prediction signal and stops the output of the low-order bit digital code based on the comparison result signal.