Abstract: A mechanism for synchronizing a multiple-circuit system, includes (a) selecting a master circuit from a plurality of circuits, the remaining circuits including at least one slave circuit, (b) receiving, at each of the plurality of circuits, input data and a local clock signal associated with the input data, (d) generating at least one control signal at the master circuit using the local clock signal of the master circuit, (e) outputting the control signal from the master circuit, (f) forwarding the control signal to the slave circuit(s), (g) looping back the control signal to the master circuit, (h) processing the input data at the slave circuit(s) using the forwarded control signal, (i) processing the input data at the master circuit using the looped-back control signal, and (j) outputting the processed data from each of the plurality of circuits.

Abstract: A built-in self test implementation for testing the speed and timing margins of the IO pins of a source synchronous IO interface (SSIO). The implementation preferably includes built-in self test logic including a pseudo-random pattern generator which is configured to generate input sequences. Buffers are connected to the IO pins, and the buffers are configured to receive the input sequences. The buffers are connected to multiple input signature registers, and the multiple input signature registers are configured to receive the input sequences from the pseudo-random pattern generator and generate signatures. Comparators are provided to compare the signatures to expected vector values and generate a pass/fail output signal. Preferably, at least one programmable delay cell is disposed between each buffer and the multiple input signature registers. The programmable delay cells provide that propagation delays can be set to perform timing margin tests.