Abstract: Methods, systems, and computer-readable media for providing an application store are presented. In some embodiments, authentication credentials of an administrative user of an application store may be received at the application store. Based on validating the authentication credentials of the administrative user, a mobile service management interface may be provided via the application store. In addition, the mobile service management interface may include at least one control that is configured to allow the administrative user to define one or more policies to be applied to at least one application that is available in the application store.

Abstract: Methods, systems, and computer-readable media for providing an application store are presented. In some embodiments, authentication credentials of an administrative user of an application store may be received at the application store. Based on validating the authentication credentials of the administrative user, a mobile service management interface may be provided via the application store. In addition, the mobile service management interface may include at least one control that is configured to allow the administrative user to define one or more policies to be applied to at least one application that is available in the application store.

Abstract: Methods, systems, and computer-readable media for providing an application store are presented. In some embodiments, a request for a software application may be received at an application store. Subsequently, the software application may be configured, at the application store, based on a single sign-on credential. The configured software application then may be provided, by the application store, to at least one recipient device associated with the single sign-on credential.

Abstract: Methods, systems, and computer-readable media for providing an application store are presented. In some embodiments, a request for updated policy information for at least one application may be received at an application store from a policy agent. Based on receiving the request, it may be determined, at the application store, whether one or more policies for the at least one application have been updated. Based on determining that the one or more policies for the at least one application have been updated, at least one policy update may be provided to the policy agent.

Abstract: Methods, systems, and computer-readable media for providing an application store are presented. In some embodiments, a request for updated policy information for at least one application may be received at an application store from a policy agent. Based on receiving the request, it may be determined, at the application store, whether one or more policies for the at least one application have been updated. Based on determining that the one or more policies for the at least one application have been updated, at least one policy update may be provided to the policy agent.

Abstract: An electronic digital governor assembly includes a case, a printed circuit board housed within said case, the printed circuit board having control circuitry configured for controlling at least one parameter of an energy production device, and a user interface including a digital display for displaying a value of the at least one parameter and at least one button for selectively adjusting the value.

Abstract: Described herein is an enterprise system including an enterprise social platform associated with an application store platform, which is accessible by a computing device in a secure manner. The enterprise social platform stores information indicating user roles within the enterprise and provides at least one social networking feature to a group of users that are associated based on the roles, where the social networking feature is associated with an enterprise application store. An application catalog system of the enterprise application store platform includes sets of enterprise applications that are available for selection by enterprise users, and the application catalog system provides access to selected enterprise applications.

Abstract: An electronic digital governor assembly includes a case, a printed circuit board housed within said case, the printed circuit board having control circuitry configured for controlling at least one parameter of an energy production device, and a user interface including a digital display for displaying a value of the at least one parameter and at least one button for selectively adjusting the value.

Abstract: A method and circuit for measuring internal pulses includes an enable circuit configured to receive a control signal from an on-chip built-in tester to enable measurement of internal circuits. A delay chain is configured to receive a pulse signal from an on-chip circuit component. Sampling latches each include a data input coupled between adjacent delay elements of the delay chain and synchronized with the clock signal such that a transition in the pulse signal is indicated by comparing adjacent digital values in an output sequence.

Abstract: The present invention is directed towards systems and methods for more efficiently managing installation of a plurality of application plug-ins for a client device. A client device executes, upon startup, a receiver application. The receiver application may manage installations of application plug-ins for a user of the client device. The receiver application may receive from an update server a delivery of application plug-ins to install on the client device. Upon receipt of the delivery, the receiver application may automatically install each of the application plug-ins on the client device transparently to the user of the client device. The receiver application may automatically start each of the application plug-ins.

Abstract: A method and circuit for measuring internal pulses includes an enable circuit configured to receive a control signal from an on-chip built-in tester to enable measurement of internal circuits. A delay chain is configured to receive a pulse signal from an on-chip circuit component. Sampling latches each include a data input coupled between adjacent delay elements of the delay chain and synchronized with the clock signal such that a transition in the pulse signal is indicated by comparing adjacent digital values in an output sequence.

Abstract: A local on-chip programmable pulsewidth and delay generating circuit includes a clock generation circuit configured to receive a global clock signal and output a local clock signal. The clock generation circuit includes a pulse shaping portion which adjusts a pulse width of the global clock signal in accordance with at least one of a trailing edge delay and a leading edge delay. The leading edge delay is generated by a leading edge delay circuit, and the trailing edge delay is generated by a trailing edge delay circuit configured to apply a delay to a trailing edge of a pulse. The trailing edge delay circuit includes a delay chain having programmable stages of delay elements, each stage being independently controlled using control bits decoded from address latches.

Abstract: A local on-chip programmable pulsewidth and delay generating circuit includes a clock generation circuit configured to receive a global clock signal and output a local clock signal. The clock generation circuit includes a pulse shaping portion which adjusts a pulse width of the global clock signal in accordance with at least one of a trailing edge delay and a leading edge delay. The leading edge delay is generated by a leading edge delay circuit, and the trailing edge delay is generated by a trailing edge delay circuit configured to apply a delay to a trailing edge of a pulse. The trailing edge delay circuit includes a delay chain having programmable stages of delay elements, each stage being independently controlled using control bits decoded from address latches.

Abstract: A method and circuit for measuring internal pulses includes an enable circuit configured to receive a control signal from an on-chip built-in tester to enable measurement of internal circuits. A delay chain is configured to receive a pulse signal from an on-chip circuit component. Sampling latches each include a data input coupled between adjacent delay elements of the delay chain and synchronized with the clock signal such that a transition in the pulse signal is indicated by comparing adjacent digital values in an output sequence.

Abstract: A local on-chip programmable pulsewidth and delay generating circuit includes a clock generation circuit configured to receive a global clock signal and output a local clock signal. The clock generation circuit includes a pulse shaping portion which adjusts a pulse width of the global clock signal in accordance with at least one of a trailing edge delay and a leading edge delay. The leading edge delay is generated by a leading edge delay circuit, and the trailing edge delay is generated by a trailing edge delay circuit configured to apply a delay to a trailing edge of a pulse. The trailing edge delay circuit includes a delay chain having programmable stages of delay elements, each stage being independently controlled using control bits decoded from address latches.

Abstract: A method and circuit for measuring internal pulses includes an enable circuit configured to receive a control signal from an on-chip built-in tester to enable measurement of internal circuits. A delay chain is configured to receive a pulse signal from an on-chip circuit component. Sampling latches each include a data input coupled between adjacent delay elements of the delay chain and synchronized with the clock signal such that a transition in the pulse signal is indicated by comparing adjacent digital values in an output sequence.

Abstract: A local on-chip programmable pulsewidth and delay generating circuit includes a clock generation circuit configured to receive a global clock signal and output a local clock signal. The clock generation circuit includes a pulse shaping portion which adjusts a pulse width of the global clock signal in accordance with at least one of a trailing edge delay and a leading edge delay. The leading edge delay is generated by a leading edge delay circuit, and the trailing edge delay is generated by a trailing edge delay circuit configured to apply a delay to a trailing edge of a pulse. The trailing edge delay circuit includes a delay chain having programmable stages of delay elements, each stage being independently controlled using control bits decoded from address latches.

Abstract: A D-Cache SRAM cell having a modified design in schematic and layout that exhibits increased symmetry from the circuit schematic and the physical cell layout perspectives. That is, the SRAM cell includes two read ports and minimizes asymmetry by provisioning one read port on a true side and one on the complement side. Asymmetry is additionally minimized in layout as cross coupling on both the true and complement sides rises up one level by providing from the local interconnect level a via connection to a M1 or metallization level. Moreover, the distance between the local interconnect (MC) and the gate conductor structure (PC) has been enlarged and equalized for each of the pFETs in the cross-latched SRAM cell. As a result, the SRAM cell has been rendered insensitive to overlay (local interconnect processing too close) by maximizing this MC-PC distance.

Abstract: A D-Cache SRAM cell having a modified design in schematic and layout that exhibits increased symmetry from the circuit schematic and the physical cell layout perspectives. That is, the SRAM cell includes two read ports and minimizes asymmetry by provisioning one read port on a true side and one on the complement side. Asymmetry is additionally minimized in layout as cross coupling on both the true and complement sides rises up one level by providing from the local interconnect level a via connection to a M1 or metallization level. Moreover, the distance between the local interconnect (MC) and the gate conductor structure (PC) has been enlarged and equalized for each of the pFETs in the cross-latched SRAM cell. As a result, the SRAM cell has been rendered insensitive to overlay (local interconnect processing too close) by maximizing this MC-PC distance.