Patents by Inventor Kevin Altair Hurd

Kevin Altair Hurd has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210048984
    Abstract: Various embodiments of the disclosure relate to an accelerated mathematical engine. In certain embodiments, the accelerated mathematical engine is applied to image processing such that convolution of an image is accelerated by using a two-dimensional matrix processor comprising sub-circuits that include an ALU, output register and shadow register. This architecture supports a clocked, two-dimensional architecture in which image data and weights are multiplied in a synchronized manner to allow a large number of mathematical operations to be performed in parallel.
    Type: Application
    Filed: May 29, 2020
    Publication date: February 18, 2021
    Inventors: Peter Joseph Bannon, Kevin Altair Hurd, Emil Talpes
  • Patent number: 10715175
    Abstract: Various embodiments of the invention provide systems, devices, and methods for decompressing encoded electronic data to increase decompression throughput using any number of decoding engines. In certain embodiments, this is accomplished by identifying and processing a next record in a pipeline operation before having to complete the decompression of a current record. Various embodiments take advantage of the knowledge of the method of how the records have been encoded, e.g., in a single long record, to greatly reduce delay time, compared with existing designs, when decompressing encoded electronic data.
    Type: Grant
    Filed: August 28, 2017
    Date of Patent: July 14, 2020
    Assignee: Tesla, Inc.
    Inventors: Peter Joseph Bannon, Kevin Altair Hurd
  • Patent number: 10671349
    Abstract: Various embodiments of the disclosure relate to an accelerated mathematical engine. In certain embodiments, the accelerated mathematical engine is applied to image processing such that convolution of an image is accelerated by using a two-dimensional matrix processor comprising sub-circuits that include an ALU, output register and shadow register. This architecture supports a clocked, two-dimensional architecture in which image data and weights are multiplied in a synchronized manner to allow a large number of mathematical operations to be performed in parallel.
    Type: Grant
    Filed: September 20, 2017
    Date of Patent: June 2, 2020
    Assignee: Tesla, Inc.
    Inventors: Peter Joseph Bannon, Kevin Altair Hurd, Emil Talpes
  • Patent number: 10416899
    Abstract: In various embodiment, the present invention teaches a sequencer that identifies an address point of a first data block within a memory and a length of data that comprises that data block and is related to an input of a matrix processor. The sequencer then calculates, based on the block length, the input length, and a memory map, a block count representative of a number of data blocks that are to be retrieved from the memory. Using the address pointer, the sequencer may retrieve a number of data blocks from the memory in a number of cycles that depends on whether the data blocks are contiguous. In embodiments, based on the length of data, a formatter then maps the data blocks to the input of the matrix processor.
    Type: Grant
    Filed: June 5, 2018
    Date of Patent: September 17, 2019
    Assignee: Tesla, Inc.
    Inventors: Peter Joseph Bannon, Kevin Altair Hurd, Emil Talpes
  • Publication number: 20190250830
    Abstract: Presented are systems and methods that allow for efficient data processing that reduce data latency and, thus, power consumption and data management cost. In various embodiments, this is accomplished by using a sequencer that identifies an address pointer of a first data block within a memory and a length of data that comprises that data block and is related to an input of a matrix processor. The sequencer then calculates, based on the block length, the input length, and a memory map, a block count representative of a number of data blocks that are to be retrieved from the memory. Using the address pointer, the sequencer may retrieve a number of data blocks from the memory in a number of cycles that depends on whether the data blocks are contiguous. In embodiments, based on the length of data, a formatter then maps the data blocks to the input of the matrix processor.
    Type: Application
    Filed: June 5, 2018
    Publication date: August 15, 2019
    Applicant: Tesla, Inc.
    Inventors: Peter Joseph BANNON, Kevin Altair HURD, Emil TALPES
  • Publication number: 20190205738
    Abstract: Described herein are systems and methods that utilize a novel hardware-based pooling architecture to process the output of a convolution engine representing an output channel of a convolution layer in a convolutional neural network (CNN). The pooling system converts the output into a set of arrays and aligns them according to a pooling operation to generate a pooling result. In certain embodiments, this is accomplished by using an aligner that aligns, e.g., over a number of arithmetic cycles, an array of data in the output into rows and shifts the rows relative to each other. A pooler applies a pooling operation to a combination of a subset of data from each row to generate the pooling result.
    Type: Application
    Filed: January 4, 2018
    Publication date: July 4, 2019
    Applicant: Tesla, Inc.
    Inventors: Peter Joseph BANNON, Kevin Altair Hurd
  • Publication number: 20190068217
    Abstract: Various embodiments of the invention provide systems, devices, and methods for decompressing encoded electronic data to increase decompression throughput using any number of decoding engines. In certain embodiments, this is accomplished by identifying and processing a next record in a pipeline operation before having to complete the decompression of a current record. Various embodiments take advantage of the knowledge of the method of how the records have been encoded, e.g., in a single long record, to greatly reduce delay time, compared with existing designs, when decompressing encoded electronic data.
    Type: Application
    Filed: August 28, 2017
    Publication date: February 28, 2019
    Applicant: Tesla, Inc.
    Inventors: Peter Joseph BANNON, Kevin Altair HURD
  • Publication number: 20190026237
    Abstract: A microprocessor system comprises a computational array and a hardware arbiter. The computational array includes a plurality of computation units. Each of the plurality of computation units operates on a corresponding value addressed from memory. The hardware arbiter is configured to control issuing of at least one memory request for one or more of the corresponding values addressed from the memory for the computation units. The hardware arbiter is also configured to schedule a control signal to be issued based on the issuing of the memory requests.
    Type: Application
    Filed: March 13, 2018
    Publication date: January 24, 2019
    Inventors: Emil Talpes, Peter Joseph Bannon, Kevin Altair Hurd
  • Publication number: 20190026078
    Abstract: Various embodiments of the disclosure relate to an accelerated mathematical engine. In certain embodiments, the accelerated mathematical engine is applied to image processing such that convolution of an image is accelerated by using a two-dimensional matrix processor comprising sub-circuits that include an ALU, output register and shadow register. This architecture supports a clocked, two-dimensional architecture in which image data and weights are multiplied in a synchronized manner to allow a large number of mathematical operations to be performed in parallel.
    Type: Application
    Filed: September 20, 2017
    Publication date: January 24, 2019
    Applicant: Tesla, Inc.
    Inventors: Peter Joseph BANNON, Kevin Altair HURD, Emil TALPES
  • Patent number: 8074057
    Abstract: Systems and methods for controlling instruction throughput are disclosed. One embodiment of a system may comprise a comparator that determines a difference value in an actual instructions per clock cycle throughput and a target instructions per clock cycle throughput setting, and a throttle control that sums a plurality of difference values to determine an average difference value over a plurality of clock cycles and adjusts the actual instructions per clock cycle throughput based on the average difference value.
    Type: Grant
    Filed: March 8, 2005
    Date of Patent: December 6, 2011
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Kevin Altair Hurd