Patents by Inventor Kevin Altair Hurd
Kevin Altair Hurd has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11893393Abstract: A microprocessor system comprises a computational array and a hardware arbiter. The computational array includes a plurality of computation units. Each of the plurality of computation units operates on a corresponding value addressed from memory. The hardware arbiter is configured to control issuing of at least one memory request for one or more of the corresponding values addressed from the memory for the computation units. The hardware arbiter is also configured to schedule a control signal to be issued based on the issuing of the memory requests.Type: GrantFiled: October 22, 2021Date of Patent: February 6, 2024Assignee: Tesla, Inc.Inventors: Emil Talpes, Peter Joseph Bannon, Kevin Altair Hurd
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Publication number: 20230305808Abstract: Various embodiments of the disclosure relate to an accelerated mathematical engine. In certain embodiments, the accelerated mathematical engine is applied to image processing such that convolution of an image is accelerated by using a two-dimensional matrix processor comprising sub-circuits that include an ALU, output register and shadow register. This architecture supports a clocked, two-dimensional architecture in which image data and weights are multiplied in a synchronized manner to allow a large number of mathematical operations to be performed in parallel.Type: ApplicationFiled: May 31, 2023Publication date: September 28, 2023Inventors: Peter Joseph Bannon, Kevin Altair Hurd, Emil Talpes
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Patent number: 11698773Abstract: Various embodiments of the disclosure relate to an accelerated mathematical engine. In certain embodiments, the accelerated mathematical engine is applied to image processing such that convolution of an image is accelerated by using a two-dimensional matrix processor comprising sub-circuits that include an ALU, output register and shadow register. This architecture supports a clocked, two-dimensional architecture in which image data and weights are multiplied in a synchronized manner to allow a large number of mathematical operations to be performed in parallel.Type: GrantFiled: July 29, 2022Date of Patent: July 11, 2023Assignee: Tesla, Inc.Inventors: Peter Joseph Bannon, Kevin Altair Hurd, Emil Talpes
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Publication number: 20220365753Abstract: Various embodiments of the disclosure relate to an accelerated mathematical engine. In certain embodiments, the accelerated mathematical engine is applied to image processing such that convolution of an image is accelerated by using a two-dimensional matrix processor comprising sub-circuits that include an ALU, output register and shadow register. This architecture supports a clocked, two-dimensional architecture in which image data and weights are multiplied in a synchronized manner to allow a large number of mathematical operations to be performed in parallel.Type: ApplicationFiled: July 29, 2022Publication date: November 17, 2022Inventors: Peter Joseph Bannon, Kevin Altair Hurd, Emil Talpes
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Patent number: 11403069Abstract: Various embodiments of the disclosure relate to an accelerated mathematical engine. In certain embodiments, the accelerated mathematical engine is applied to image processing such that convolution of an image is accelerated by using a two-dimensional matrix processor comprising sub-circuits that include an ALU, output register and shadow register. This architecture supports a clocked, two-dimensional architecture in which image data and weights are multiplied in a synchronized manner to allow a large number of mathematical operations to be performed in parallel.Type: GrantFiled: May 29, 2020Date of Patent: August 2, 2022Assignee: Tesla, Inc.Inventors: Peter Joseph Bannon, Kevin Altair Hurd, Emil Talpes
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Publication number: 20220188123Abstract: A microprocessor system comprises a computational array and a hardware arbiter. The computational array includes a plurality of computation units. Each of the plurality of computation units operates on a corresponding value addressed from memory. The hardware arbiter is configured to control issuing of at least one memory request for one or more of the corresponding values addressed from the memory for the computation units. The hardware arbiter is also configured to schedule a control signal to be issued based on the issuing of the memory requests.Type: ApplicationFiled: October 22, 2021Publication date: June 16, 2022Inventors: Emil Talpes, Peter Joseph Bannon, Kevin Altair Hurd
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Patent number: 11157287Abstract: A microprocessor system comprises a computational array and a hardware arbiter. The computational array includes a plurality of computation units. Each of the plurality of computation units operates on a corresponding value addressed from memory. The hardware arbiter is configured to control issuing of at least one memory request for one or more of the corresponding values addressed from the memory for the computation units. The hardware arbiter is also configured to schedule a control signal to be issued based on the issuing of the memory requests.Type: GrantFiled: March 13, 2018Date of Patent: October 26, 2021Assignee: Tesla, Inc.Inventors: Emil Talpes, Peter Joseph Bannon, Kevin Altair Hurd
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Publication number: 20210048984Abstract: Various embodiments of the disclosure relate to an accelerated mathematical engine. In certain embodiments, the accelerated mathematical engine is applied to image processing such that convolution of an image is accelerated by using a two-dimensional matrix processor comprising sub-circuits that include an ALU, output register and shadow register. This architecture supports a clocked, two-dimensional architecture in which image data and weights are multiplied in a synchronized manner to allow a large number of mathematical operations to be performed in parallel.Type: ApplicationFiled: May 29, 2020Publication date: February 18, 2021Inventors: Peter Joseph Bannon, Kevin Altair Hurd, Emil Talpes
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Patent number: 10715175Abstract: Various embodiments of the invention provide systems, devices, and methods for decompressing encoded electronic data to increase decompression throughput using any number of decoding engines. In certain embodiments, this is accomplished by identifying and processing a next record in a pipeline operation before having to complete the decompression of a current record. Various embodiments take advantage of the knowledge of the method of how the records have been encoded, e.g., in a single long record, to greatly reduce delay time, compared with existing designs, when decompressing encoded electronic data.Type: GrantFiled: August 28, 2017Date of Patent: July 14, 2020Assignee: Tesla, Inc.Inventors: Peter Joseph Bannon, Kevin Altair Hurd
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Patent number: 10671349Abstract: Various embodiments of the disclosure relate to an accelerated mathematical engine. In certain embodiments, the accelerated mathematical engine is applied to image processing such that convolution of an image is accelerated by using a two-dimensional matrix processor comprising sub-circuits that include an ALU, output register and shadow register. This architecture supports a clocked, two-dimensional architecture in which image data and weights are multiplied in a synchronized manner to allow a large number of mathematical operations to be performed in parallel.Type: GrantFiled: September 20, 2017Date of Patent: June 2, 2020Assignee: Tesla, Inc.Inventors: Peter Joseph Bannon, Kevin Altair Hurd, Emil Talpes
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Patent number: 10416899Abstract: In various embodiment, the present invention teaches a sequencer that identifies an address point of a first data block within a memory and a length of data that comprises that data block and is related to an input of a matrix processor. The sequencer then calculates, based on the block length, the input length, and a memory map, a block count representative of a number of data blocks that are to be retrieved from the memory. Using the address pointer, the sequencer may retrieve a number of data blocks from the memory in a number of cycles that depends on whether the data blocks are contiguous. In embodiments, based on the length of data, a formatter then maps the data blocks to the input of the matrix processor.Type: GrantFiled: June 5, 2018Date of Patent: September 17, 2019Assignee: Tesla, Inc.Inventors: Peter Joseph Bannon, Kevin Altair Hurd, Emil Talpes
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Publication number: 20190250830Abstract: Presented are systems and methods that allow for efficient data processing that reduce data latency and, thus, power consumption and data management cost. In various embodiments, this is accomplished by using a sequencer that identifies an address pointer of a first data block within a memory and a length of data that comprises that data block and is related to an input of a matrix processor. The sequencer then calculates, based on the block length, the input length, and a memory map, a block count representative of a number of data blocks that are to be retrieved from the memory. Using the address pointer, the sequencer may retrieve a number of data blocks from the memory in a number of cycles that depends on whether the data blocks are contiguous. In embodiments, based on the length of data, a formatter then maps the data blocks to the input of the matrix processor.Type: ApplicationFiled: June 5, 2018Publication date: August 15, 2019Applicant: Tesla, Inc.Inventors: Peter Joseph BANNON, Kevin Altair HURD, Emil TALPES
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Publication number: 20190205738Abstract: Described herein are systems and methods that utilize a novel hardware-based pooling architecture to process the output of a convolution engine representing an output channel of a convolution layer in a convolutional neural network (CNN). The pooling system converts the output into a set of arrays and aligns them according to a pooling operation to generate a pooling result. In certain embodiments, this is accomplished by using an aligner that aligns, e.g., over a number of arithmetic cycles, an array of data in the output into rows and shifts the rows relative to each other. A pooler applies a pooling operation to a combination of a subset of data from each row to generate the pooling result.Type: ApplicationFiled: January 4, 2018Publication date: July 4, 2019Applicant: Tesla, Inc.Inventors: Peter Joseph BANNON, Kevin Altair Hurd
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Publication number: 20190068217Abstract: Various embodiments of the invention provide systems, devices, and methods for decompressing encoded electronic data to increase decompression throughput using any number of decoding engines. In certain embodiments, this is accomplished by identifying and processing a next record in a pipeline operation before having to complete the decompression of a current record. Various embodiments take advantage of the knowledge of the method of how the records have been encoded, e.g., in a single long record, to greatly reduce delay time, compared with existing designs, when decompressing encoded electronic data.Type: ApplicationFiled: August 28, 2017Publication date: February 28, 2019Applicant: Tesla, Inc.Inventors: Peter Joseph BANNON, Kevin Altair HURD
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Publication number: 20190026078Abstract: Various embodiments of the disclosure relate to an accelerated mathematical engine. In certain embodiments, the accelerated mathematical engine is applied to image processing such that convolution of an image is accelerated by using a two-dimensional matrix processor comprising sub-circuits that include an ALU, output register and shadow register. This architecture supports a clocked, two-dimensional architecture in which image data and weights are multiplied in a synchronized manner to allow a large number of mathematical operations to be performed in parallel.Type: ApplicationFiled: September 20, 2017Publication date: January 24, 2019Applicant: Tesla, Inc.Inventors: Peter Joseph BANNON, Kevin Altair HURD, Emil TALPES
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Publication number: 20190026237Abstract: A microprocessor system comprises a computational array and a hardware arbiter. The computational array includes a plurality of computation units. Each of the plurality of computation units operates on a corresponding value addressed from memory. The hardware arbiter is configured to control issuing of at least one memory request for one or more of the corresponding values addressed from the memory for the computation units. The hardware arbiter is also configured to schedule a control signal to be issued based on the issuing of the memory requests.Type: ApplicationFiled: March 13, 2018Publication date: January 24, 2019Inventors: Emil Talpes, Peter Joseph Bannon, Kevin Altair Hurd
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Patent number: 8074057Abstract: Systems and methods for controlling instruction throughput are disclosed. One embodiment of a system may comprise a comparator that determines a difference value in an actual instructions per clock cycle throughput and a target instructions per clock cycle throughput setting, and a throttle control that sums a plurality of difference values to determine an average difference value over a plurality of clock cycles and adjusts the actual instructions per clock cycle throughput based on the average difference value.Type: GrantFiled: March 8, 2005Date of Patent: December 6, 2011Assignee: Hewlett-Packard Development Company, L.P.Inventor: Kevin Altair Hurd