Abstract: Apparatus and method to reduce the duration of timeout periods in fault-tolerant distributed computer systems. When nodes execute a task redundantly and communicate their results over a network for further processing, it is customary to calculate timeouts on a worst-case basis, thereby prolonging their duration unnecessarily. By applying Tchebychev's inequality, which holds for any statistical distribution, to adaptively determine the distribution of the arrival times of the results at the point where further processing of those results takes place, the duration of timeouts is reduced. Successively refining the statistical distribution of the arrival times leads to an improved forecast of future arrivals. Thus timeouts are kept to a minimum without compromising the reliability of the system.

Abstract: Computing modules can cooperate to tolerate faults among their members. In a preferred embodiment, computing modules couple with dual-ported memories and interface with a dynamically reconfigurable Field-Programmable Gate Array ("FPGA"). The FPGA serves as a computational engine to provide direct hardware support for flexible fault tolerance between unconstrained combinations of the computing modules. In addition to supporting traditional fault tolerance functions that require bit-for-bit exactness, the FPGA engine is programmed to tolerate faults that cannot be detected through direct comparison of module outputs. Combating these faults requires more complex algorithmic or heuristic approaches that check whether outputs meet user-defined reasonableness criteria. For example, forming a majority from outputs that are not identical but may nonetheless be correct requires taking an inexact vote.