Abstract: In certain aspects, an apparatus includes a first gating circuit having an input and an output, wherein the input of the first gating circuit is configured to receive a first clock signal. The apparatus also includes a delay circuit having an input and an output, wherein the input of the delay circuit is coupled to the output of the first gating circuit. The apparatus further includes a control circuit configured to receive an enable signal, detect a logic state at the output of the delay circuit, and cause the first gating circuit to pass or gate the first clock signal based on the enable signal and the detected logic state at the output of the delay circuit.

Abstract: A dual-edge aware clock divider configured to generate an output clock based on the input clock and a ratio of an integer M over an integer N is disclosed herein. The frequency of the output clock is based on a frequency of the input clock multiplied by the ratio (M/N), wherein M may be set to a range up to N. The output clock includes M pulses within a sequence time window having a length of N periods of the input clock. The output clock includes one or more rising edges that are substantially time aligned with one or more rising edges and one or more falling edges of the input clock, respectively. The dual-edge aware clock divider is configured to generate the output clock based on inverted and non-inverted portions of the input clock. A hybrid clock divider including the dual-edge and single-edge aware techniques is provided.

Abstract: A dual-edge aware clock divider configured to generate an output clock based on the input clock and a ratio of an integer M over an integer N is disclosed herein. The frequency of the output clock is based on a frequency of the input clock multiplied by the ratio (M/N), wherein M may be set to a range up to N. The output clock includes M pulses within a sequence time window having a length of N periods of the input clock. The output clock includes one or more rising edges that are substantially time aligned with one or more rising edges and one or more falling edges of the input clock, respectively. The dual-edge aware clock divider is configured to generate the output clock based on inverted and non-inverted portions of the input clock. A hybrid clock divider including the dual-edge and single-edge aware techniques is provided.

Abstract: A dual-edge aware clock divider configured to generate an output clock based on the input clock and a ratio of an integer M over an integer N is disclosed herein. The frequency of the output clock is based on a frequency of the input clock multiplied by the ratio (M/N), wherein M may be set to a range up to N. The output clock includes M pulses within a sequence time window having a length of N periods of the input clock. The output clock includes one or more rising edges that are substantially time aligned with one or more rising edges and one or more falling edges of the input clock, respectively. The dual-edge aware clock divider is configured to generate the output clock based on inverted and non-inverted portions of the input clock. A hybrid clock divider including the dual-edge and single-edge aware techniques is provided.

Abstract: A system is provided that controls the clocking of a processor depending upon its usage of execution units. As the processor transitions from a default mode of operation using a default number of the execution units to an increased load mode of operation using an increased number of the execution units, a current drawn by the processor from a power rail remains substantially unchanged.

Abstract: A system is provided that controls the clocking of a processor depending upon its usage of execution units. As the processor transitions from a default mode of operation using a default number of the execution units to an increased load mode of operation using an increased number of the execution units, a current drawn by the processor from a power rail remains substantially unchanged.

Abstract: A clock signal generator including a fractional clock divider and a frequency ramp control circuit. The fractional clock divider is configured to generate an output clock signal with a frequency being a divider ratio multiplied by a frequency of an input clock signal. The frequency ramp control circuit is configured to provide the fractional clock divider a set of divider ratios so that the frequency of the output clock signal is ramped in steps from a current frequency to a target frequency. The frequency ramp control circuit is configured to produce frequency change steps each having substantially the same duration. The frequency ramp control circuit is also configured to provide the set of divider ratios such as a first portion of the frequency ramp is performed using coarse frequency changes and a second portion of the ramp is performed using at least one fine frequency change.

Abstract: A clock signal generator including a fractional clock divider and a frequency ramp control circuit. The fractional clock divider is configured to generate an output clock signal with a frequency being a divider ratio multiplied by a frequency of an input clock signal. The frequency ramp control circuit is configured to provide the fractional clock divider a set of divider ratios so that the frequency of the output clock signal is ramped in steps from a current frequency to a target frequency. The frequency ramp control circuit is configured to produce frequency change steps each having substantially the same duration. The frequency ramp control circuit is also configured to provide the set of divider ratios such as a first portion of the frequency ramp is performed using coarse frequency changes and a second portion of the ramp is performed using at least one fine frequency change.

Abstract: A clock signal generator including a fractional clock divider and a frequency ramp control circuit. The fractional clock divider is configured to generate an output clock signal with a frequency being a divider ratio multiplied by a frequency of an input clock signal. The frequency ramp control circuit is configured to provide the fractional clock divider a set of divider ratios so that the frequency of the output clock signal is ramped in steps from a current frequency to a target frequency. The frequency ramp control circuit is configured to produce frequency change steps each having substantially the same duration. The frequency ramp control circuit is also configured to provide the set of divider ratios such as a first portion of the frequency ramp is performed using coarse frequency changes and a second portion of the ramp is performed using at least one fine frequency change.