Abstract: The present invention generally relates to the field of fluid management procedures for the treatment of fluid management disorders in a patient, and related components and methods. In particular, the present invention is directed to bearing arrangements used in intravascular blood pump assembly designed and configured to generate low bearing interfacial resistive force when operated in a blood or plasma protein containing environment.

Abstract: Methods and systems for using a clot retrieval device for treating a clot in a blood vessel for use in the treatment of ischemic stroke to achieve a clinically effective revascularization or perfusion rate for clots comprising a higher ratio of red blood cells to fibrin.

Abstract: Herein is reported a method for determining the concentration of a therapeutic antibody in a tissue of an experimental animal to whom the therapeutic antibody had been administered, wherein the interference from residual blood in a tissue sample of the experimental animal, which is used for determining the concentration of the therapeutic antibody in said tissue, is reduced, wherein the concentration of the therapeutic antibody in the tissue of the experimental animal is calculated with the following formula: C tmAb , t ? i ? s ? s ? u ? e = C t ? mAb , tissue , det . C tissue , sample - C refmAb , tissue , det . C tissue , sample C refmAb , plasma , det . * C tmAb , plasma , det . wherein CtmAb,tissue,det.=obtained by determining the concentration of the therapeutic antibody in the tissue sample of the experimental animal, CtmAb,plasma,det.

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed for sparse tensor storage for neural network accelerators. An example apparatus includes sparsity map generating circuitry to generate a sparsity map corresponding to a tensor, the sparsity map to indicate whether a data point of the tensor is zero, static storage controlling circuitry to divide the tensor into one or more storage elements, and a compressor to perform a first compression of the one or more storage elements to generate one or more compressed storage elements, the first compression to remove zero points of the one or more storage elements based on the sparsity map and perform a second compression of the one or more compressed storage elements, the second compression to store the one or more compressed storage elements contiguously in memory.

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to debug a hardware accelerator such as a neural network accelerator for executing Artificial Intelligence computational workloads. An example apparatus includes a core with a core input and a core output to execute executable code based on a machine-learning model to generate a data output based on a data input, and debug circuitry coupled to the core. The debug circuitry is configured to detect a breakpoint associated with the machine-learning model, compile executable code based on at least one of the machine-learning model or the breakpoint. In response to the triggering of the breakpoint, the debug circuitry is to stop the execution of the executable code and output data such as the data input, data output and the breakpoint for debugging the hardware accelerator.

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed for sparse tensor storage for neural network accelerators. An example apparatus includes sparsity map generating circuitry to generate a sparsity map corresponding to a tensor, the sparsity map to indicate whether a data point of the tensor is zero, static storage controlling circuitry to divide the tensor into one or more storage elements, and a compressor to perform a first compression of the one or more storage elements to generate one or more compressed storage elements, the first compression to remove zero points of the one or more storage elements based on the sparsity map and perform a second compression of the one or more compressed storage elements, the second compression to store the one or more compressed storage elements contiguously in memory.

Abstract: Herein is reported a method for determining the concentration of a therapeutic antibody in a tissue of an experimental animal to whom the therapeutic antibody had been administered, wherein the interference from residual blood in a tissue sample of the experimental animal, which is used for determining the concentration of the therapeutic antibody in said tissue, is reduced by applying an inert reference antibody that does not penetrate into said tissue, whereby the inert reference antibody is administered 2 to 10 minutes prior to obtaining the tissue and blood sample.

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed that increase data reuse for multiply and accumulate (MAC) operations. An example apparatus includes a MAC circuit to process a first context of a set of a first type of contexts stored in a first buffer and a first context of a set of a second type of contexts stored in a second buffer. The example apparatus also includes control logic circuitry to, in response to determining that there is an additional context of the second type to be processed in the set of the second type of contexts, maintain the first context of the first type in the first buffer. The control logic circuitry is also to, in response to determining that there is an additional context of the first type to be processed in the set of the first type of contexts maintain the first context of the second type in the second buffer and iterate a pointer of the second buffer from a first position to a next position in the second buffer.

Abstract: A rail panel includes a first rail and a second rail. The first rail includes a first pair of side walls, a first perimeter wall disposed orthogonally to the first pair of side walls, and a pair of internal walls extending from the first perimeter wall and disposed parallel to the first pair of side walls. The first perimeter wall defines a plurality of first cable holes spaced apart along the length of the first perimeter wall. The second rail includes a second pair of side walls, and a second perimeter wall disposed orthogonally to the second pair of side walls, the second perimeter wall defining a plurality of second cable holes disposed spaced apart along the length of the second perimeter wall. A plurality of vertical cables extend from the first rail to the second rail, where a first end of each of the plurality of vertical cables extends through a respective first cable hole and a second end of each of the plurality of vertical cables extends through a respective second cable hole.

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to debug a hardware accelerator such as a neural network accelerator for executing Artificial Intelligence computational workloads. An example apparatus includes a core with a core input and a core output to execute executable code based on a machine-learning model to generate a data output based on a data input, and debug circuitry coupled to the core. The debug circuitry is configured to detect a breakpoint associated with the machine-learning model, compile executable code based on at least one of the machine-learning model or the breakpoint. In response to the triggering of the breakpoint, the debug circuitry is to stop the execution of the executable code and output data such as the data input, data output and the breakpoint for debugging the hardware accelerator.

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed that increase data reuse for multiply and accumulate (MAC) operations. An example apparatus includes a MAC circuit to process a first context of a set of a first type of contexts stored in a first buffer and a first context of a set of a second type of contexts stored in a second buffer. The example apparatus also includes control logic circuitry to, in response to determining that there is an additional context of the second type to be processed in the set of the second type of contexts, maintain the first context of the first type in the first buffer. The control logic circuitry is also to, in response to determining that there is an additional context of the first type to be processed in the set of the first type of contexts maintain the first context of the second type in the second buffer and iterate a pointer of the second buffer from a first position to a next position in the second buffer.

Abstract: The invention provides humanized anti-human Tau(pS422) antibodies and methods of using the same.

Abstract: A masking film includes an adhesion layer that includes a blend of hydrogenated styrene block copolymer and low density polyethylene. The adhesion layer has an outer adhesion surface configured to contact a substrate. The outer adhesion surface has an average surface roughness Ra of between 100 nm and 350 nm, and an average spacing between peaks Sm of between 20 ?m and 150 ?m. The masking film also includes a release layer on a side of the adhesion layer opposite the outer adhesion surface.

Abstract: A rail panel includes a top rail defining a plurality of fastener receiving holes and a plurality of top cable holes. The rail panel includes a bottom rail defining a plurality of bottom cable holes and a plurality of clip receiving holes. The rail panel includes a plurality of vertical cables extending from the top rail to the bottom rail. The rail panel includes a plurality of threaded swage fittings, each coupled to a respective top end of one of the plurality of vertical cables, and a plurality of clip receiving swage fittings, each coupled to a respective bottom end of one of the plurality of vertical cables, and a plurality of clips, each received by a respective clip receiving swage fitting.

Abstract: A compute block includes a DMA engine that reads data from an external memory and write the data into a local memory of the compute block. An MAC array in the compute block may use the data to perform convolutions. The external memory may store weights of one or more filters in a memory layout that comprises a sequence of sections for each filter. Each section may correspond to a channel of the filter and may store all the weights in the channel. The DMA engine may convert the memory layout to a different memory layout, which includes a sequence of new sections for each filter. Each new section may include a weight vector that includes a sequence of weights, each of which is from a different channel. The DMA engine may also compress the weights, e.g., by removing zero valued weights, before the conversion of the memory layout.

Abstract: One or more network tests for a network are selected, wherein the selected one or more network tests simulate an attempt to establish an anomalous network configuration. A network configuration update is generated based on the selected one or more network tests and the network configuration update is issued to a network-based device. A performance of the network is monitored for establishment of the anomalous network configuration in response to the network configuration update and a configuration of the network is revised based on the monitored performance of the network, to mitigate the establishment of the anomalous network configuration.

Abstract: The invention provides humanized anti-human Tau(pS422) antibodies and methods of using the same.

Abstract: An DNN accelerator includes a DMA engine that can rearrange weight data layout. The DMA engine may read a weight tensor from a memory (e.g., DRAM). The weight tensor includes weights arranged in a 3D matrix. The DMA engine may partition the weight tensor into a plurality of virtual banks based on a structure of a PE array, e.g., based on the number of activated PE columns in the PE array. Then the DMA engine may partition a virtual bank into a plurality of virtual sub-banks. The DMA engine may also identify data blocks from different ones of the plurality of virtual sub-banks. A data block may include a plurality of input channels and may have a predetermined spatial size and storage size. The DMA engine form a linear data structure by interleaving the data blocks. The DMA engine can write the linear data structure into another memory (e.g., SRAM).

Abstract: The present invention relates generally to a device which is directed toward a compact, portable, lightweight and modular device for the integrity testing of equipment to determine fluid pressure, temperature and flow rates at specific locations throughout a system. The present invention provides the ability and capability to acquire data via immediate, intermediate or distanced pressure and temperature monitoring, observation and collection. Said results may be directly monitored, at an immediate, intermediate or distanced proximity, and thereby collected and digitally stored and/or transmitted, via real-time data collection and transmission, to an on-site or off-site operator or manager for remote active or passive data collection, data monitoring, data analysis and data management.

Abstract: Sparsity processing within a compute block can be done on unpacked data. The compute block includes a sparsity decoder that generates a combined sparsity vector from an activation sparsity vector and a weight sparsity vector. The activation sparsity vector indicates positions of non-zero valued activations in an activation context. The weight sparsity vector indicates positions of non-zero valued weights in a weight context. The combined sparsity vector comprises one or more zero valued bits and one or more non-zero valued bits. The sparsity decoder may determine the position of a non-zero valued bit in the combined sparsity vector and determine an address for the non-zero valued activation and the non-zero valued weight based on the position of the non-zero valued bit. The non-zero valued activation and the non-zero valued weight may be provided to a PE for performing MAC operations.