Abstract: Exosomes are a small type of extracellular vesicles containing nucleic acids, lipids, and proteins that are implicated in tumorigenesis, metastasis, and cardiac regeneration, and therefore serve as potentially useful biomarkers from fluids or as vehicles for drug delivery. Global bottom-up mass spectrometry-based proteomics has been previously used to profile exosome cargo for diagnostic purposes. However, the current protocols for MS analysis of extracellular vesicles and exosome proteomics are challenging due to labor-intensive sample preparation, including lengthy digestion times and removal of MS incompatible reagents, and the need for high sensitivity. To address these challenges, the present invention provides a novel, high-throughput strategy for extracellular vesicle analysis and exosome proteomics using a photo-cleavable, anionic surfactant, preferably 4-hexylphenylazosulfonate (Azo).

Abstract: In one embodiment, an electronic device comprises a plurality of electrical switches and a plurality of energy storage elements arrayed relative to one another such that the energy storage elements may be connected in series, or in parallel, or both, to an input and an output.

Abstract: A shifter circuit comprises, in one embodiment, an input voltage divider stage comprising multiple transistors arranged in a transistor stack defining a plurality of intermediate nodes. The transistor stack is connected between an input signal and ground and has at least one output. An inverting buffer stage is connected to a supply voltage and coupled to the input voltage divider's output. The inverting buffer stage is configured to provide an inverted output signal. Means are provided for stepping up the inverted output signal, receiving a stepped up output signal and providing a level-shifted output signal at a voltage level lower than that of the input signal.

Abstract: A shifter circuit comprises a high and low voltage buffer stages and an output buffer stage. The high voltage buffer stage comprises multiple transistors arranged in a transistor stack having a plurality of intermediate nodes connecting individual transistors along the stack. The transistor stack is connected between a voltage level being shifted to and an input voltage. An inverter of this stage comprises multiple inputs and an output. Inverter inputs are connected to a respective intermediate node of the transistor stack. The low voltage buffer stage has an input connected to the input voltage and an output, and is operably connected to the high voltage buffer stage. The low voltage buffer stage is connected between a voltage level being shifted away from and a lower voltage. The output buffer stage is driven by the outputs of the high voltage buffer stage inverter and the low voltage buffer stage.

Abstract: Shifter circuits comprise a matched translation stack comprising at least first and second stacks each of which comprising multiple transistors. The matched translation stack is configured to provide a primary logic level shift between a voltage level away from which a shift is desired (VddL) and a voltage level to which the shift is desired (VddH). One or more high voltage buffer stages are provided, at least one of which being connected with and biased by the matched translation stack. At least one high voltage buffer stage comprises multiple transistors arranged in a transistor stack that is biased by the first stack of the matched translation stack, and is connected to receive an input supplied by the second stack of the matched translation stack. The high voltage buffer stage also comprises an inverter that drives an output stage which is also driven by a low voltage buffer stage.