Patents by Inventor Kevin C. Gotze
Kevin C. Gotze has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230019372Abstract: Various techniques related to authenticating and verifying the integrity of data received by a computer system from an external source (such as a sensor) are disclosed. Hardware circuits are disclosed that, along with the computer processor, allow for error-checking and authentication of data received by the computer system. For instance, the hardware circuits may generate a separate authentication code that can be compared to the authentication code in the data itself to determine whether or not the message is authentic and whether or not there is an error in the data. The disclosed techniques reduce the processing requirements of a computer system and can be implemented using simple hardware circuit designs.Type: ApplicationFiled: July 13, 2021Publication date: January 19, 2023Inventors: Paul A. Baker, Michael W. Murphy, Mark P. Colosky, James E. Zmuda, Jangwon Lee, Kevin C. Gotze, Peter Louis Bielawski
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Patent number: 9946875Abstract: In one embodiment, a processor includes at least one execution unit and Return Oriented Programming (ROP) detection logic. The ROP detection logic may determine a ROP metric based on a plurality of control transfer events. The ROP detection logic may also determine whether the ROP metric exceeds a threshold. The ROP detection logic may also, in response to a determination that the ROP metric exceeds the threshold, provide a ROP attack notification.Type: GrantFiled: January 5, 2017Date of Patent: April 17, 2018Assignee: Intel CorporationInventors: Stephen A. Fischer, Kevin C. Gotze, Yuriy Bulygin, Kirk D. Brannock
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Patent number: 9742563Abstract: A method, of an aspect, includes challenging a set of Physically Unclonable Function (PUF) cells, of an integrated circuit device, and receiving a set of PUF bits from the PUF cells in response. A PUF key is generated based on the set of PUF bits. An encryption of the PUF key with an embedded key is output from the integrated circuit device. The integrated circuit device receives an encryption of a fuse key with the PUF key. Fuses of the integrated circuit device are programmed with at least one of the fuse key and the received encryption of the fuse key with the PUF key. Other methods, apparatus, and systems are also disclosed.Type: GrantFiled: September 28, 2012Date of Patent: August 22, 2017Assignee: Intel CorporationInventors: Kevin C. Gotze, Gregory M. Iovino, Jiangtao Li
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Publication number: 20170116414Abstract: In one embodiment, a processor includes at least one execution unit and Return Oriented Programming (ROP) detection logic. The ROP detection logic may determine a ROP metric based on a plurality of control transfer events. The ROP detection logic may also determine whether the ROP metric exceeds a threshold. The ROP detection logic may also, in response to a determination that the ROP metric exceeds the threshold, provide a ROP attack notification.Type: ApplicationFiled: January 5, 2017Publication date: April 27, 2017Inventors: Stephen A. Fischer, Kevin C. Gotze, Yuriy Bulygin, Kirk D. Brannock
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Patent number: 9582663Abstract: In one embodiment, a processor includes at least one execution unit and Return Oriented Programming (ROP) detection logic. The ROP detection logic may determine a ROP metric based on a plurality of control transfer events. The ROP detection logic may also determine whether the ROP metric exceeds a threshold. The ROP detection logic may also, in response to a determination that the ROP metric exceeds the threshold, provide a ROP attack notification.Type: GrantFiled: December 7, 2015Date of Patent: February 28, 2017Assignee: Intel CorporationInventors: Stephen A. Fischer, Kevin C. Gotze, Yuriy Bulygin, Kirk D. Brannock
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Publication number: 20160085966Abstract: In one embodiment, a processor includes at least one execution unit and Return Oriented Programming (ROP) detection logic. The ROP detection logic may determine a ROP metric based on a plurality of control transfer events. The ROP detection logic may also determine whether the ROP metric exceeds a threshold. The ROP detection logic may also, in response to a determination that the ROP metric exceeds the threshold, provide a ROP attack notification.Type: ApplicationFiled: December 7, 2015Publication date: March 24, 2016Inventors: Stephen A. Fischer, Kevin C. Gotze, Yuriy Bulygin, Kirk D. Brannock
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Patent number: 9251348Abstract: In one embodiment, a processor includes at least one execution unit and Return Oriented Programming (ROP) detection logic. The ROP detection logic may determine a ROP metric based on a plurality of control transfer events. The ROP detection logic may also determine whether the ROP metric exceeds a threshold. The ROP detection logic may also, in response to a determination that the ROP metric exceeds the threshold, provide a ROP attack notification.Type: GrantFiled: March 13, 2013Date of Patent: February 2, 2016Assignee: Intel CorporationInventors: Stephen A. Fischer, Kevin C. Gotze, Yuriy Bulygin, Kirk D. Brannock
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Patent number: 9223979Abstract: In one embodiment, a processor includes at least one execution unit and Return Oriented Programming (ROP) detection logic. The ROP detection logic may determine a ROP metric based on a plurality of control transfer events. The ROP detection logic may also determine whether the ROP metric exceeds a threshold. The ROP detection logic may also, in response to a determination that the ROP metric exceeds the threshold, provide a ROP attack notification.Type: GrantFiled: October 31, 2012Date of Patent: December 29, 2015Assignee: Intel CorporationInventors: Stephen A. Fischer, Kevin C. Gotze, Yuriy Bulygin, Kirk D. Brannock
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Patent number: 8928347Abstract: An integrated circuit substrate of an aspect includes a plurality of exposed electrical contacts. The integrated circuit substrate also includes an inaccessible set of Physically Unclonable Function (PUF) cells to generate an inaccessible set of PUF bits that are not accessible through the exposed electrical contacts. The integrated circuit substrate also includes an accessible set of PUF cells to generate an accessible set of PUF bits that are accessible through the exposed electrical contacts. Other apparatus, methods, and systems are also disclosed.Type: GrantFiled: September 28, 2012Date of Patent: January 6, 2015Assignee: Intel CorporationInventors: Kevin C. Gotze, Gregory M. Iovino, Jiangtao Li, David Johnston, Sanu K. Mathew, George W. Cox, Anand Rajan
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Patent number: 8885819Abstract: Embodiments of an invention for fuse attestation to secure the provisioning of secret keys during integrated circuit manufacturing are disclosed. In one embodiment, an apparatus includes a storage location, a physically unclonable function (PUF) circuit, a PUF key generator, an encryption unit, and a plurality of fuses. The storage location is to store a configuration fuse value. The PUF circuit is to provide a PUF value. The PUF key generator is to generate a PUF key based on the PUF value. The encryption unit is to encrypt the configuration fuse value using the PUF key. The PUF key and the configuration fuse value are to be provided to a key server. The key server is to determine that the configuration fuse value indicates that the apparatus is a production component, and, in response, provide a fuse key to be stored in the plurality of fuses.Type: GrantFiled: December 27, 2012Date of Patent: November 11, 2014Assignee: Intel CorporationInventors: Kevin C. Gotze, Jiangtao Li, Gregory M. Iovino
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Publication number: 20140185795Abstract: Embodiments of an invention for fuse attestation to secure the provisioning of secret keys during integrated circuit manufacturing are disclosed. In one embodiment, an apparatus includes a storage location, a physically unclonable function (PUF) circuit, a PUF key generator, an encryption unit, and a plurality of fuses. The storage location is to store a configuration fuse value. The PUF circuit is to provide a PUF value. The PUF key generator is to generate a PUF key based on the PUF value. The encryption unit is to encrypt the configuration fuse value using the PUF key. The PUF key and the configuration fuse value are to be provided to a key server. The key server is to determine that the configuration fuse value indicates that the apparatus is a production component, and, in response, provide a fuse key to be stored in the plurality of fuses.Type: ApplicationFiled: December 27, 2012Publication date: July 3, 2014Inventors: Kevin C. Gotze, Jiangtao Li, Gregory M. Iovino
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Publication number: 20140123281Abstract: In one embodiment, a processor includes at least one execution unit and Return Oriented Programming (ROP) detection logic. The ROP detection logic may determine a ROP metric based on a plurality of control transfer events. The ROP detection logic may also determine whether the ROP metric exceeds a threshold. The ROP detection logic may also, in response to a determination that the ROP metric exceeds the threshold, provide a ROP attack notification.Type: ApplicationFiled: October 31, 2012Publication date: May 1, 2014Inventors: Stephen A. Fischer, Kevin C. Gotze, Yuriy Bulygin, Kirk D. Brannock
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Publication number: 20140123286Abstract: In one embodiment, a processor includes at least one execution unit and Return Oriented Programming (ROP) detection logic. The ROP detection logic may determine a ROP metric based on a plurality of control transfer events. The ROP detection logic may also determine whether the ROP metric exceeds a threshold. The ROP detection logic may also, in response to a determination that the ROP metric exceeds the threshold, provide a ROP attack notification.Type: ApplicationFiled: March 13, 2013Publication date: May 1, 2014Inventors: Stephen A. Fischer, Kevin C. Gotze, Yuriy Bulygin, Kirk D. Brannock
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Publication number: 20140091832Abstract: An integrated circuit substrate of an aspect includes a plurality of exposed electrical contacts. The integrated circuit substrate also includes an inaccessible set of Physically Unclonable Function (PUF) cells to generate an inaccessible set of PUF bits that are not accessible through the exposed electrical contacts. The integrated circuit substrate also includes an accessible set of PUF cells to generate an accessible set of PUF bits that are accessible through the exposed electrical contacts. Other apparatus, methods, and systems are also disclosed.Type: ApplicationFiled: September 28, 2012Publication date: April 3, 2014Inventors: Kevin C. Gotze, Gregory M. Iovino, Jiangtao Li, David Johnston, Sanu K. Mathew, George W. Cox, Anand Rajan
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Publication number: 20140093074Abstract: A method, of an aspect, includes challenging a set of Physically Unclonable Function (PUF) cells, of an integrated circuit device, and receiving a set of PUF bits from the PUF cells in response. A PUF key is generated based on the set of PUF bits. An encryption of the PUF key with an embedded key is output from the integrated circuit device. The integrated circuit device receives an encryption of a fuse key with the PUF key. Fuses of the integrated circuit device are programmed with at least one of the fuse key and the received encryption of the fuse key with the PUF key. Other methods, apparatus, and systems are also disclosed.Type: ApplicationFiled: September 28, 2012Publication date: April 3, 2014Inventors: Kevin C. Gotze, Gregory M. Iovino, Jiangtao Li
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Patent number: 7953987Abstract: A method and apparatus is disclosed for preventing the unintended retention of secret data caused by preferred state/burn-in in secure electronic modules. Sequentially storing the data and its inverse on alternating clock cycles, and by actively overwriting it to destroy it, prevents SRAM devices from developing a preferred state. By encrypting a relatively large amount of secret data with a master encryption key, and storing said master key in this non-preferred state storage, the electronic module conveniently extends this protection scheme to a large amount of data, without the overhead of investing or actively erasing the larger storage area.Type: GrantFiled: March 6, 2007Date of Patent: May 31, 2011Assignee: International Business Machines CorporationInventors: Carl U. Buscaglia, Vincenzo Condorelli, Kevin C. Gotze, Nihad Hadzic, Donald W. Plass, Tamas Visegrady
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Patent number: 7768005Abstract: A physically secure processing assembly is provided that includes dies mounted on a substrate so as to sandwich the electrical contacts of the dies between the dies and the substrate. The substrate is provided with substrate contacts and conductive pathways that are electrically coupled to the die contacts and extend through the substrate. Electrical conductors surround the conductive pathways. A monitoring circuit detects a break in continuity of one or more of the electrical conductors, and preferably renders the assembly inoperable. Preferably, an epoxy encapsulation is provided to prevent probing tools from being able to reach the die or substrate contacts.Type: GrantFiled: May 29, 2008Date of Patent: August 3, 2010Assignee: International Business Machines CorporationInventors: Vincenzo Condorelli, Claudius Feger, Kevin C. Gotze, Nihad Hadzic, John U. Knickerbocker, Edmund J. Sprogis
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Patent number: 7765445Abstract: System-accessible frequency measuring circuits and procedures permit on-chip testing of the oscillators and provide test results observable off chip via LSSD scan paths. This allows a rapid ensemble of ring oscillators in a standard ASIC test flow without the need for on chip analog test equipment (the test apparatus has effectively been created on device and can be digitally configured, operated and read). Frequency measuring logic that can 1) functionally operate to measure the frequency of the ring oscillators; 2) participate in traditional logical tests such as LSSD and LBIST to verify that the circuit is manufactured correctly and is likely to operate and 3) operate in a special ring-oscillator test mode, that allows the logic to operate on a tester very similarly to the way it does functionally. In this mode, the frequency measuring logic can be scanned to a specific state, started by pulsing a digital I/O, and the measured analog value can be scanned out sometime later after the test has completed.Type: GrantFiled: February 16, 2008Date of Patent: July 27, 2010Assignee: International Business Machines CorporationInventors: Joseph E. Eckelman, Kevin C. Gotze, James A. Kyle, Jennifer Yuk Sim Yan
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Patent number: 7703201Abstract: A method for embedding tamper proof layers and discrete components into a printed circuit board stack-up is disclosed. According to this method, a plating mask is applied on a base substrate to cover partially one of its faces. Conductive ink is then spread on this face so as to fill the gap formed by the plating mask. To obtain a uniform distribution of the conductive ink and then gel it, the conductive ink is preferably heated. A dielectric layer is applied on the conductive ink layer and the polymerization process is ended to obtain a strong adhesion between these two layers. In a preferred embodiment, conductive tracks are simultaneously designed on the other face of the base substrate to reduce thermo-mechanical strains and deformations.Type: GrantFiled: October 25, 2005Date of Patent: April 27, 2010Assignee: International Business Machines CorporationInventors: Stefano Sergio Oggioni, Vincenzo Condorelli, Nihad Hadzic, Kevin C. Gotze, Tamas Visegrady
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Publication number: 20090210760Abstract: System-accessible frequency measuring circuits and procedures permit on-chip testing of the oscillators and provide test results observable off chip via LSSD scan paths. This allows a rapid ensemble of ring oscillators in a standard ASIC test flow without the need for on chip analog test equipment (the test apparatus has effectively been created on device and can be digitally configured, operated and read). Frequency measuring logic that can 1) functionally operate to measure the frequency of the ring oscillators; 2) participate in traditional logical tests such as LSSD and LBIST to verify that the circuit is manufactured correctly and is likely to operate and 3) operate in a special ring-oscillator test mode, that allows the logic to operate on a tester very similarly to the way it does functionally. In this mode, the frequency measuring logic can be scanned to a specific state, started by pulsing a digital I/O, and the measured analog value can be scanned out sometime later after the test has completed.Type: ApplicationFiled: February 16, 2008Publication date: August 20, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Joseph E. Eckelman, Kevin C. Gotze, James A. Kyle, Jennifer Yuk Sim Yan