Abstract: A multi-product avionics control and display unit (CDU). In implementations, the CDU may include a display and a processor coupled with the display. The processor is configurable to operate in a first mode to cause the display to present standby primary flight information associated with the aircraft and a second mode to control and display operation of one or more aircraft systems associated with the aircraft.

Abstract: A multi-product avionics control and display unit (CDU). In implementations, the CDU may include a display and a processor coupled with the display. The processor is configurable to operate in a first mode to cause the display to present standby primary flight information associated with the aircraft and a second mode to control and display operation of one or more aircraft systems associated with the aircraft.

Abstract: The disclosure describes a method and system for dynamically adjusting the output power level in each channel of a multichannel mobile cellular to satellite telecommunication system, the power levels of the voice and data channels being preset to appropriate initial output power levels, the initial power level for data channels being higher than the initial power level for voice channels. The method includes receiving a call request from communication equipment on one of the plurality of channels; determining whether the call is a voice call or a data call, determining whether a transmission channel is available for the call; assigning the call to an available voice or data transmission channel; looking up pre-stored power parameters for each active transmission channel; transmitting the parameters to each active transmission channel via a message; and dynamically adjusting the output power of each active transmission channel in response to the transmitted parameters.

Abstract: A dynamic clock mode switch (11) is provided for switching clock frequencies while allowing continuing operation of a depending system. The switch includes an enable circuit for transmitting an enable signal, a phase-locked loop circuit (PLL) (15) for locking onto an input clock frequency in response to said enable circuit, a PLL lock indicator for receiving a PLL lock signal (29) from said PLL, and a clock multiplexer with a multiplier for multiplying said input clock frequency by a predetermined factor in response to said enable circuit and PLL clock signals.

Abstract: A dynamic clock indicator (11) is provided for indicating the operating mode of a dynamically clocked system. The clock indicator includes a status pin (13) and a status circuit (15) for indicating status of a variable CPU clock. The status circuit provides a status or mode signal to the status pin.