Abstract: Having a fast method to perform impairment evaluation is useful for many networks. A method or corresponding apparatus according to an example embodiment of the present invention maintains a traffic engineering database of values representing characteristics of links in the network through storage of integer values representing advertised optical signal capabilities of links between the multiple optical nodes. The example embodiment determines a path through the network for optical wavelengths to be supported by the links represented in the database as a function of evaluating optical signal characteristics at each link along a possible path using the advertised optical signal capabilities and provides a selected path meeting an acceptable integrity of the optical wavelengths to a path establishment module to establish the path through the optical network. Example embodiments significantly reduce computational complexity associated with impairment evaluation and path selection in an optical network.

Abstract: Having a fast method to perform impairment evaluation is useful for many networks. A method or corresponding apparatus according to an example embodiment of the present invention maintains a traffic engineering database of values representing characteristics of links in the network through storage of integer values representing advertised optical signal capabilities of links between the multiple optical nodes. The example embodiment determines a path through the network for optical wavelengths to be supported by the links represented in the database as a function of evaluating optical signal characteristics at each link along a possible path using the advertised optical signal capabilities and provides a selected path meeting an acceptable integrity of the optical wavelengths to a path establishment module to establish the path through the optical network. Example embodiments significantly reduce computational complexity associated with impairment evaluation and path selection in an optical network.

Abstract: An error checking circuit is provided for a digital transmission system having a dual, redundant, bus structure. The error checking circuit generates a two rail logic output having complementary states in the absence of an error, and non-complementary states in response to an error on the buses. The circuit is also self-checking in that internal failures are transmitted to the output as an error indication. The circuit is actively exercised in the absence of an error to prevent silent failures. The circuit can identify which of the buses has failed, for the most common types of failures.

Abstract: An error detection circuit detects prolonged sequences of unchanged logic state in a data busing structure. The circuit generates a complementary two rail logic output from a pair of flip-flops. The circuit includes a comparator which compares the logic state of the data input from the bus with the output of one of the flip-flops, and which inputs alternate opposite logic states to that flip-flop as long as the data input exists for a time in the same logic state as the output of the one flip-flop during a cycle. The complementary two rail output changes every cycle to actively exercise the error detection circuit and prevent silent failures therein. The circuit is self-checking because internal failures yield non-complementary outputs.

Abstract: A circuit for detecting and synchronizing an incoming signal to a reference clock wherein the incoming signal has a slightly lower frequency and may be variable in frequency with respect to the reference clock frequency. The output from this synchronizer will be stable during the first half-cycle of the reference clock and may vary during the second half-cycle of the reference clock.