Abstract: A synchronous flash memory includes an array of non-volatile memory cells. The memory device has a package configuration that is compatible with an SDRAM. The memory device can comprise an array of memory cells having N addressable sectors, and control circuitry to control erase or write operations on the array of memory cells. Protection circuitry can be coupled to the control circuitry to selectively prevent erase or write operations from being performed on both first and last sectors of the N addressable sectors. The protection circuitry can comprise a multi-bit register having a first bit corresponding to the first sector and a second bit corresponding to the last sector.

Abstract: A flash memory has erase blocks aligned primarily with array rows and secondarily with array rows. This architecture allows data to be stored across numerous pages without risking accidental erasure caused by crossing multiple erase blocks. As a result, non-volatile memory devices to be more easily substituted for volatile memory devices. In one embodiment, a flash memory includes an array of memory cells that have a plurality of adjacent pages. Addresses of the memory cells are scrambled within the pages to define erase blocks that cross the page boundaries.

Abstract: An improved memory device and architecture has been detailed that enhances a Flash memory device that has an SDRAM compatible interface. The memory device employs a virtual paging scheme that allows the memory to have an efficient Flash internal structure, while logically re-mapping this architecture externally to a compatible virtual SDRAM architecture. This allows for access and operation of the improved memory device with a compatible SDRAM controller device, while Flash specific functions can be performed with an SDRAM command sequence. Internal to the memory, memory array banks are divided into four equal segments by row range and logically re-mapped by placing the segments virtually beside each other. This forms a virtual memory bank structure of equivalent rows and columns as a comparable SDRAM device. Additionally, the improved memory device may also have an extended interface that allows for direct access to the internal Flash memory architecture without logical abstraction.

Abstract: An improved memory device and architecture has been detailed that enhances a Flash memory device that has an SDRAM compatible interface. The memory device employs a virtual paging scheme that allows the memory to have an efficient Flash internal structure, while logically re-mapping this architecture externally to a compatible virtual SDRAM architecture. This allows for access and operation of the improved memory device with a compatible SDRAM controller device, while Flash specific functions can be performed with an SDRAM command sequence. Internal to the memory, memory array banks are divided into four equal segments by row range and logically re-mapped by placing the segments virtually beside each other. This forms a virtual memory bank structure of equivalent rows and columns as a comparable SDRAM device. Additionally, the improved memory device may also have an extended interface that allows for direct access to the internal Flash memory architecture without logical abstraction.

Abstract: A flash memory has erase blocks aligned primarily with array rows and secondarily with array rows. This architecture allows data to be stored across numerous pages without risking accidental erasure caused by crossing multiple erase blocks. As a result, non-volatile memory devices to be more easily substituted for volatile memory devices. In one embodiment, a flash memory includes an array of memory cells that have a plurality of adjacent pages. Addresses of the memory cells are scrambled within the pages to define erase blocks that cross the page boundaries.

Abstract: A flash memory has an interface corresponding to a DDR DRAM. The memory samples commands and addresses on a rising edge of a clock signal. The read and write data are provided on both the rising edge and the falling edge of the clock signal.

Abstract: A flash memory has been described that can be coupled to an SDRAM controller that performs address scrambling. The flash memory includes a programmable address de-scrambler. The de-scrambler can be programmed to de-scramble primarily row addresses, including bank addresses, to maintain a common erase block location for sequential data. The present invention reduces the possibility of writing contiguous data to multiple erase blocks. The de-scrambler can be implemented as a programmable switch. The switch includes a routing circuit that can be programmed in a non-volatile manner.

Abstract: A flash memory has been described that has an interface corresponding to a rambus dynamic random access memory (RDRAM). The memory samples commands and addresses on a rising edge of a clock signal. The read and write data are provided on both the rising edge and the falling edge of the clock signal.

Abstract: A flash memory has been described that can be coupled to an SDRAM controller that performs address scrambling. The flash memory includes a programmable address de-scrambler. The de-scrambler can be programmed to de-scramble primarily row addresses, including bank addresses, to maintain a common erase block location for sequential data. The present invention reduces the possibility of writing contiguous data to multiple erase blocks. The de-scrambler can be implemented as a programmable switch. The switch includes a routing circuit that can be programmed in a non-volatile manner.

Abstract: A flash memory has an interface corresponding to a DDR DRAM. The memory samples commands and addresses on a rising edge of a clock signal. The read and write data are provided on both the rising edge and the falling edge of the clock signal.

Abstract: An improved memory device and architecture has been detailed that enhances a Flash memory device that has an SDRAM compatible READ interface. The memory device employs a virtual paging scheme that allows for the architecture of the memory to implement an efficient Flash memory structure internally. Externally, the memory logically maps the internal Flash architecture to an SDRAM compatible interface and virtual architecture, allowing for memory access and operation with a compatible SDRAM controller device. Programming, erasing, block protection, and other Flash specific functions differ from SDRAM and are performed with an SDRAM command sequence. A memory device may have four times as many rows in a memory array bank as a comparable SDRAM device, but only one fourth as many columns. This reduces the number of sense amplifiers activating, therefore saving power and complexity in the memory device.

Abstract: An improved memory device and architecture has been detailed that enhances a Flash memory device that has an SDRAM compatible interface. The memory device employs a virtual paging scheme that allows for the architecture of the memory to implement an efficient Flash memory structure internally. Externally, the memory logically maps the internal Flash architecture to an SDRAM compatible interface and virtual architecture, allowing for memory access and operation with a compatible SDRAM controller device. A double data rate interface is provided to allow data to be input and output from the memory in synchronization with both rising and falling edges of a clock signal.