Abstract: A network computer system receives request data from computing devices of requesting users in a sub-region of a service area. The system further receives location data from computing devices of drivers operating in the sub-region. Based on the request data and the location data, the system determines a service condition for the sub-region. Based on the service condition indicating that the sub-region is in a driver oversupply state, the system transmits a service instruction to computing devices of a plurality of drivers within the sub-region, the service instruction being associated with a target outside the sub-region and a set of progress conditions. The system then periodically determines, for each driver of the plurality of drivers, an estimated time of arrival (ETA) to the target from a current position of the driver to determine whether the driver is satisfying the set of progress conditions of the service instruction.

Abstract: Systems and methods for vehicle telematics registration are provided. One embodiment of a method includes receiving a vehicle identifier for a vehicle and a user telephone number for a user from a vehicle head unit, where the vehicle head unit provided a user interface requesting the user telephone number. Similarly, some embodiments include populating a portion of a registration form for a telematics service with the vehicle identifier and the user telephone number, creating a link to the registration form, and inserting the link into an electronic message to the user telephone number. Still some embodiments include sending the electronic message to the user telephone number and registering, by the computing device, the vehicle for the telematics service in response to the user selecting the link and submitting the registration form.

Abstract: Systems and methods for vehicle telematics registration are provided. One embodiment of a method includes receiving a vehicle identifier for a vehicle and a user telephone number for a user from a vehicle head unit, where the vehicle head unit provided a user interface requesting the user telephone number. Similarly, some embodiments include populating a portion of a registration form for a telematics service with the vehicle identifier and the user telephone number, creating a link to the registration form, and inserting the link into an electronic message to the user telephone number. Still some embodiments include sending the electronic message to the user telephone number and registering, by the computing device, the vehicle for the telematics service in response to the user selecting the link and submitting the registration form.

Abstract: In one embodiment, the present invention includes a frequency divider circuit for dividing the frequency of an input signal by an odd value. In one embodiment, a frequency divider circuit includes a counter configured to receive a clock input signal and a divisor having an odd value. The counter counts clock cycles up to the divisor to generate a count. A control circuit is configured to receive the count, the divisor, and the clock input signal and generate one or more control signals to control a state of a clock output signal. A half cycle adjust circuit is configured to receive the clock input signal and the one or more control signals from the control circuit and provide an additional one-half cycle adjustment of the clock output signal. The frequency divider circuit may be a feed forward circuit with fast startup characteristics.

Abstract: Present invention provides a method and apparatus for generating multiple phase shifted clocks with clocks delayed from EFM clock.

Abstract: A digital clock generator uses an on-chip digital delay chain to generate clock signal with variable frequency. An external charging circuit with variable charge rate may be used to select target frequency by generating digital pulse with variable width. An external reference clock may be used to calibrate the digital clock frequency. The external reference clock may be enabled only for calibration.

Abstract: A system and method for generating sample control signals for a sample and hold circuit used to control access to optical media is provided. The sample control signals are generated with sufficient duration (width) to adequately sample a reflected laser power signal. The sample control signals are defined relative to a laser power command signal generated in response to an internal data stream, rather than directly in response to the internal data stream, thereby allowing for more precise control of the sample control signals. As a result, substantial portions of each pulse of the reflected laser power signal can be sampled, without sampling transition noise that exists when the reflected laser power signal changes states. Generating the sample control signals from a laser power command signal, rather than the input data signal, more accurately time shifts the sampling command to the reflected laser power.

Abstract: A memory module and a method for accessing the same are proposed. The memory module comprises a memory, a transmission selection port connected to input of the memory, a first data output port and a second data output port connected to output of the memory. The transmission selection port input one of a first address signal and a second address signal to the memory according to a logical level of a first clock signal. The first data output port and the second data output port access data of memory designated by the first address signal or the second address signal according to the logical level of the first clock signal.

Abstract: The present invention relates to a cooling system of a furnace, and more particularly, to a multi-cycle cooling system, located by the furnace door. The multi-cycle cooling system comprises the first gas cooling cycle, the second gas cooling cycle, the first liquid cooling cycle, the second liquid cooling cycle, the heat sinks and the heat insulation slot. When inside the process tube proceeds the high temperature process like depositing process, the first gas cooling cycle and the second gas cooling cycle are opened and the second liquid cooling cycle is closed at the same time. The second gas cooling cycle and the second liquid cooling cycle are assembled in the first flange, which is located on the process tube and contacts with the door. The first liquid cooling cycle in the second flange, which is located on the process tube and contacts with the first range, is always opened.

Abstract: Method and system for compensating for a segment length of one or more of three consecutive mark and space segments utilized in a computer system. The three segments are received at a first pre-processor, the first segment is separated and issued separately from the remaining two segments, and the first segment length is compared with a permitted range of lengths. If the first segment length is not within the permitted range, a first error signal is issued, preferably indicating the non-complying first length. This process is repeated at second and third pre-processors. A segment processor receives the three individual segments and the error signals and non-complying lengths, if any, and compensates or corrects for any non-complying segment lengths before further processing occurs.

Abstract: A QFN (Quad Flat Non-leaded) semiconductor packaging technology is proposed, which can be used to package a semiconductor chip of a central-pad type having at least one row of bond pads arranged along a center line on one surface of the semiconductor chip. The proposed semiconductor packaging technology is based on a specially-designed leadframe which is formed with a plurality of leads, a chip-support-and-grounding structure, and at least one ground wing; wherein the chip-support-and-grounding structure serves both as a die pad and a ground bus for the packaged chip, and the ground wing is electrically linked to the chip-support-and-grounding structure. After encapsulation process is completed, the ground wing as well as the outer lead portions are exposed to the bottom outside of the encapsulation body, which can be then bonded a PCB's ground plane during SMT (Surface Mount Technology) process, thus enhancing the grounding effect and the electrical performance of the packaged chip during operation.

Abstract: Method and system for determining varying widths of each of a sequence of signal components (marks and spaces) in an incoming digital signal stream and for indicating which mark widths and which space widths fall outside acceptable ranges. A pre-mark and pre-space are added to the front end of the recieved stream for alignment purposes. The width of each signal component (mark or space) is determined and compared with an acceptable range of mark widths or space widths. Each mark or space that lies outside an acceptable range has an indicium associated with this mark or space, indicating this non-compliance. The modified digital signal stream, including the indicia, is re-issued after a selected time delay for subsequent signal processing. A method for measurement or estimation of mark width and space width is presented.

Abstract: A system and method for generating sample control signals for a sample and hold circuit used to control access to optical media is provided. The sample control signals are generated with sufficient duration (width) to adequately sample a reflected laser power signal. The sample control signals are defined relative to a laser power command signal generated in response to an internal data stream, rather than directly in response to the internal data stream, thereby allowing for more precise control of the sample control signals. As a result, substantial portions of each pulse of the reflected laser power signal can be sampled, without sampling transition noise that exists when the reflected laser power signal changes states. Generating the sample control signals from a laser power command signal, rather than the input data signal, more accurately time shifts the sampling command to the reflected laser power.

Abstract: Method and system for receiving each data element of an array once and simultaneously forming an EDC error detection term, two ECC P-parity checkbytes and two ECC-Q-parity checkbytes for the array. Each data element is read once from memory and is received by an EDC processor, by an ECC-P processor and by an ECC-Q processor and is processed in parallel and substantially simultaneously by the three processors to form an EDC error detection term and the ECC-P-parity and ECC-Q-parity checkbytes, using shift registers with feed-back and/or weighted summation of selected register contents.

Abstract: A versatile serial to parallel interface capable of both receiving multiple types of input formats and operating in multiple operational modes includes a multiplexer, a signal generator, and a register. The multiplexer receives serial data from a plurality of possible data sources and, in response to a set of selection signals, outputs one of the sets of serial data to the signal generator. The signal generator thereafter forwards the serial data to the register for storage. In addition to forwarding the serial data to the register, the signal generator also generates clock and control signals. These signals are used to control the operation of the register to ensure proper serial to parallel conversion of the input serial data. In addition, these signals may also be provided to the source of the serial data to control the actions of the data source. The signal generator generates the clock and control signals in response to indication information provided to the signal generator.

Abstract: Method and system for receiving each data element of an N×M array once and simultaneously forming an EDC error detection term and two ECC P-parity checkbytes for the array. Each data element is read once from memory and is received by an EDC processor and by an ECC processor and processed in parallel by the two processors to form the EDC error detection term and two ECC P-parity checkbytes.

Abstract: A method for set-up of a group of parameter values needed in a CD-R or CD-RW write cycle, where the time allotted for set-up is as low as six clock cycles. In a clock cycle from a preceding write cycle, first and second parameter values are read into first and second registers, and a third parameter value is read into a first SRAM. In clock cycles 1-5 of the present write cycle, fourth, fifth, sixth, seventh and eighth parameter values are read into second, third, fourth, fifth and sixth SRAMs. In clock cycle no. 6 or later of the present write cycle, three sums (or differences) of selected combinations of these eight parameter values are calculated and stored, new first and second parameter values are read into first and second registers, and a new third parameter value is read into another SRAM. The method is generalized to K parameters stored in registers, N parameters stored in SRAMs and calculation of M selected linear combinations of the K+N parameter values.

Abstract: A semiconductor package with an exposed heat spreader includes a substrate having a semiconductor chip adhered to a first surface of the substrate. The heat spreader includes an upper portion, a lower portion with an opening formed in the center for receiving the semiconductor chip, and a connecting portion for connecting the upper portion and the lower portion in a manner that the upper portion is raised to a height above the opening of the lower portion. The lower portion is formed with a plurality of positioning members outwardly extending from edges of the lower portion to prevent the heat spreader from being dislocated during a molding process, and further includes downward flutes formed on the periphery of the opening for enabling resin flow underneath the heat spreader. The upper portion of the heat spreader is exposed to an exterior of the semiconductor package to improve heat dissipation.

Abstract: A method for computing Reed-Solomon error control checkbytes in reduced time and with reduced gate count. Two syndromes, s0 and s1, are computed for a sequence of data elements, using a selected primitive &agr; that satisfies a selected primitive polynomial relation p(&agr;)=0. Each of two checkbytes, c0 and c1, is expressed as a linear combination of the syndromes s0 and s1, where each coefficient of each linear combination is expressed as a single power of the primitive &agr; and is stored at the checkbyte generator for multiple use. This approach reduces gate count and associated time delay in formation of the usual Reed-Solomon multiplier coefficients.

Abstract: A QFN (Quad Flat Non-leaded) semiconductor packaging technology is proposed, which can be used to package a semiconductor chip of a central-pad type having at least one row of bond pads arranged along a center line on one surface of the semiconductor chip. The proposed semiconductor packaging technology is based on a specially-designed leadframe which is formed with a plurality of leads, a chip-support-and-grounding structure, and at least one ground wing; wherein the chip-support-and-grounding structure serves both as a die pad and a ground bus for the packaged chip, and the ground wing is electrically linked to the chip-support-and-grounding structure. After encapsulation process is completed, the ground wing as well as the outer lead portions are exposed to the bottom outside of the encapsulation body, which can be then bonded a PCB's ground plane during SMT (Surface Mount Technology) process, thus enhancing the grounding effect and the electrical performance of the packaged chip during operation.