Patents by Inventor Kevin Ching

Kevin Ching has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250112122
    Abstract: Integrated circuit (IC) devices and systems with backside power gates, and methods of forming the same, are disclosed herein. In one embodiment, an integrated circuit die includes a device layer with one or more transistors, a first interconnect over the device layer, a second interconnect under the device layer, and one or more power gates under the device layer.
    Type: Application
    Filed: September 29, 2023
    Publication date: April 3, 2025
    Applicant: INTEL CORPORATION
    Inventors: Kevin P. O'Brien, Paul Gutwin, David L. Kencke, Mahmut Sami Kavrik, Daniel Chanemougame, Ashish Verma Penumatcha, Carl Hugo Naylor, Kirby Maxey, Uygar E. Avci, Tristan A. Tronic, Chelsey Dorow, Andrey Vyatskikh, Rachel A. Steinhardt, Chia-Ching Lin, Chi-Yin Cheng, Yu-Jin Chen, Tyrone Wilson
  • Publication number: 20250113540
    Abstract: Techniques and mechanisms for providing gate dielectric structures of a transistor. In an embodiment, the transistor comprises a thin channel structure which comprises one or more layers of a transition metal dichalcogenide (TMD) material. The channel structure forms two surfaces on opposite respective sides thereof, wherein the surfaces extend to each of two opposing edges of the channel structure. A composite gate dielectric structure comprises first bodies of a first dielectric material, wherein the first bodies each adjoin a different respective one of the two opposing edges, and variously extend to each of the surfaces two surfaces. The composite gate dielectric structure further comprises another body of a second dielectric material other than the first dielectric material. In another embodiment, the other body adjoins one or both of the two surfaces, and extends along one or both of the two surfaces to each of the first bodies.
    Type: Application
    Filed: September 29, 2023
    Publication date: April 3, 2025
    Applicant: Intel Corporation
    Inventors: Carl H. Naylor, Rachel Steinhardt, Mahmut Sami Kavrik, Chia-Ching Lin, Andrey Vyatskikh, Kevin O’Brien, Kirby Maxey, Ashish Verma Penumatcha, Uygar Avci, Matthew Metz, Chelsey Dorow
  • Publication number: 20250113547
    Abstract: Integrated circuit structures having internal spacers for 2D channel materials, and methods of fabricating integrated circuit structures having internal spacers for 2D channel materials, are described. For example, an integrated circuit structure includes a stack of two-dimensional (2D) material nanowires. A gate structure is vertically around the stack of 2D material nanowires. Internal gate spacers are between vertically adjacent ones of the stack of 2D material nanowires and laterally adjacent to the gate structure. The 2D material nanowires are recessed relative to the internal gate spacers. Conductive contact structures are at corresponding ends of the stack of 2D material nanowires, the conductive contact structures adjacent to the internal gate spacers and vertically overlapping with the internal gate spacers.
    Type: Application
    Filed: September 29, 2023
    Publication date: April 3, 2025
    Inventors: Chia-Ching LIN, Tao CHU, Chiao-Ti HUANG, Guowei XU, Robin CHAO, Feng ZHANG, Yue ZHONG, Yang ZHANG, Ting-Hsiang HUNG, Kevin P. O’BRIEN, Uygar E. AVCI, Carl H. NAYLOR, Mahmut Sami KAVRIK, Andrey VYATSKIKH, Rachel STEINHARDT, Chelsey DOROW, Kirby MAXEY
  • Publication number: 20250113573
    Abstract: A low strain transfer protective layer is formed on a transition metal dichalcogenide (TMD) monolayer to enable the transfer of the TMD monolayer from a growth substrate to a target substrate with little or no strain-induced damage to the TMD monolayer. Transfer of a TMD monolayer from a growth substrate to a target substrate comprises two transfers, a first transfer from the growth substrate to a carrier wafer and a second transfer from the carrier wafer to the target substrate. Transfer of the TMD monolayer from the growth substrate to the carrier wafer comprises mechanically lifting off the TMD monolayer from the growth substrate. The low strain transfer protective layer can limit the amount of strain transferred from the carrier wafer to the TMD monolayer during lift-off. The carrier wafer and protective layer are separated from the TMD monolayer after attachment of the TMD monolayer to the target substrate.
    Type: Application
    Filed: September 29, 2023
    Publication date: April 3, 2025
    Applicant: Intel Corporation
    Inventors: Andrey Vyatskikh, Paul B. Fischer, Uygar E. Avci, Chelsey Dorow, Mahmut Sami Kavrik, Karthik Krishnaswamy, Chia-Ching Lin, Jennifer Lux, Kirby Maxey, Carl Hugo Naylor, Kevin P. O'Brien, Justin R. Weber
  • Patent number: 12266712
    Abstract: A transistor includes a first channel layer over a second channel layer, where the first and the second channel layers include a monocrystalline transition metal dichalcogenide (TMD). The transistor structure further includes a source structure coupled to a first end of the first and second channel layers, a drain structure coupled to a second end of the first and second channel layers, a gate structure between the source material and the drain material, and between the first channel layer and the second channel layer. The transistor further includes a spacer laterally between the gate structure and the and the source structure and between the gate structure and the drain structure. A liner is between the spacer and the gate structure. The liner is in contact with the first channel layer and the second channel layer and extends between the gate structure and the respective source structure and the drain structure.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: April 1, 2025
    Assignee: Intel Corporation
    Inventors: Ashish Verma Penumatcha, Kevin O'Brien, Chelsey Dorow, Kirby Maxey, Carl Naylor, Tanay Gosavi, Sudarat Lee, Chia-Ching Lin, Seung Hoon Sung, Uygar Avci
  • Patent number: 12266720
    Abstract: Transistor structures with monocrystalline metal chalcogenide channel materials are formed from a plurality of template regions patterned over a substrate. A crystal of metal chalcogenide may be preferentially grown from a template region and the metal chalcogenide crystals then patterned into the channel region of a transistor. The template regions may be formed by nanometer-dimensioned patterning of a metal precursor, a growth promoter, a growth inhibitor, or a defected region. A metal precursor may be a metal oxide suitable, which is chalcogenated when exposed to a chalcogen precursor at elevated temperature, for example in a chemical vapor deposition process.
    Type: Grant
    Filed: December 21, 2020
    Date of Patent: April 1, 2025
    Assignee: Intel Corporation
    Inventors: Carl Naylor, Chelsey Dorow, Kevin O'Brien, Sudarat Lee, Kirby Maxey, Ashish Verma Penumatcha, Tanay Gosavi, Patrick Theofanis, Chia-Ching Lin, Uygar Avci, Matthew Metz, Shriram Shivaraman
  • Publication number: 20250107147
    Abstract: Hybrid bonding interconnect (HBI) architectures for scalability. Embodiments implement a bonding layer on a semiconductor die that includes a thick oxide layer overlaid with a thin layer of a hermetic material including silicon and at least one of carbon and nitrogen. The conductive bonds of the semiconductor die are placed in the thick oxide layer and exposed at the surface of the hermetic material. Some embodiments implement a non-bonding moisture seal ring (MSR) structure.
    Type: Application
    Filed: September 27, 2023
    Publication date: March 27, 2025
    Applicant: Intel Corporation
    Inventors: Mahmut Sami Kavrik, Uygar E. Avci, Pratyush P. Buragohain, Chelsey Dorow, Jack T. Kavalieros, Chia-Ching Lin, Matthew V. Metz, Wouter Mortelmans, Carl Hugo Naylor, Kevin P. O'Brien, Ashish Verma Penumatcha, Carly Rogan, Rachel A. Steinhardt, Tristan A. Tronic, Andrey Vyatskikh
  • Patent number: 12250784
    Abstract: A method and a device for locking an equipment with a rack are presented. The device may include a trigger and an equipment locking mechanism, wherein upon the trigger automatically activates the equipment locking mechanism upon contacting a portion of the rack. The automatic locking initiates when the equipment reaches a desired position within the rack.
    Type: Grant
    Filed: December 20, 2022
    Date of Patent: March 11, 2025
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Chia-Ching Huang, Kevin Buana, Anand Avinash Kulkarni
  • Patent number: 9547666
    Abstract: Location graph-based derivation of user attributes is disclosed. In various embodiments, location data associated with a user, such as a current and/or past location at which the user has been, is received. A user attribute data associated with the location data is determined and used to update a user profile associated with the user.
    Type: Grant
    Filed: October 31, 2014
    Date of Patent: January 17, 2017
    Assignee: NinthDecimal, Inc.
    Inventors: Kevin Ching, Grigory Sokol, Ahmad Fairiz Azizi, Luke Gain, Yury Zhyshko, Mark Dixon, Robert Abusaidi, Kevin McKenzie, John Raymond Klein, Leonid Blyukher, Jeff Pittelkau, David Staas
  • Publication number: 20160027055
    Abstract: Combining attributes from multiple sources is disclosed. Location data of a mobile device is received. The location data is mapped to a location boundary of a defined location. It is determined that a user profile is associated with the defined location based at least in part on the mapping and one or more location-based rules. The user profile is updated to include third-party data associated with the defined location.
    Type: Application
    Filed: July 23, 2014
    Publication date: January 28, 2016
    Inventors: Mark Dixon, Kevin Ching, Ahmad Fairiz Azizi, Robert Abusaidi, Leonid Blyukher, David Staas, Keith Kilpatrick, Veronica Milenkiy
  • Publication number: 20150348095
    Abstract: Measuring advertising effectiveness is disclosed. Attribute data included in a first user profile may be used to select a second user profile that is substantially similar to the first user profile. First behavior information may be determined based at least in part on an association between the first user profile and a location associated with an advertising content data. The first user profile may include an indication of exposure to the advertising content data and the second user profile does not. Second behavior information may be determined based at least in part on an association between the second user profile and the location. An advertising effectiveness value may be generated based at least in part on the first behavior information and the second behavior information.
    Type: Application
    Filed: June 3, 2014
    Publication date: December 3, 2015
    Inventors: Mark Dixon, Kevin Ching, David Staas, Keith Kilpatrick, Leonid Blyukher, Veronica Milenkiy
  • Publication number: 20150052132
    Abstract: Location graph-based derivation of user attributes is disclosed. In various embodiments, location data associated with a user, such as a current and/or past location at which the user has been, is received. A user attribute data associated with the location data is determined and used to update a user profile associated with the user.
    Type: Application
    Filed: October 31, 2014
    Publication date: February 19, 2015
    Inventors: Kevin Ching, Grigory Sokol, Ahmad Fairiz Azizi, Luke Gain, Yury Zhyshko, Mark Dixon, Robert Abusaidi, Kevin McKenzie, John Raymond Klein, Leonid Blyukher, Jeff Pittelkau, David Staas
  • Publication number: 20140012806
    Abstract: Location graph-based derivation of user attributes is disclosed. In various embodiments, location data associated with a user, such as a current and/or past location at which the user has been, is received. A user attribute data associated with the location data is determined and used to update a user profile associated with the user.
    Type: Application
    Filed: June 21, 2013
    Publication date: January 9, 2014
    Inventors: Kevin Ching, Grigory Sokol, Ahmad Fairiz Azizi, Luke Gain, Yury Zhyshko, Mark Dixon, Robert Abusaidi, Kevin McKenzie, John Raymond Klein, Leonid Blyukher, Jeff Pittelkau, David Staas
  • Publication number: 20040062036
    Abstract: The present invention relates to a pen structure, more particularly, a pen with the functions of illumination and logo indication, which comprises a main body and an illuminant, wherein the lower portion of the main body is a pen instrument for writing and the upper portion is a housing member with a lateral aperture. The inner surface of the housing member is reflective. The illuminant consists of a transparent barrel, a LED, a push-button switch, a plurality of batteries and a tail cap. The functions of illumination and logo indication can be served respectively by the interactive reflection of the inner surface while placing the illuminant from different ends thereof in the housing member.
    Type: Application
    Filed: September 27, 2002
    Publication date: April 1, 2004
    Inventor: Kevin Ching-Yi Kuo