Patents by Inventor Kevin Chou

Kevin Chou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11560498
    Abstract: A continuous process for making a pressure-sensitive adhesive is disclosed. A mixture comprising natural rubber having a Mooney viscosity of 85 to 100, a tackifier, a filler, and 0.1 to 5 wt. % of an added C12-C24 fatty acid based on the amount of mixture is masticated in a first section of a single- or twin-screw extruder. Mastication of the mixture continues in at least one subsequent extruder section in the presence of additional tackifier. The product is a homogeneous, reduced-viscosity pressure-sensitive adhesive. The minor proportion of added C12-C24 fatty acid aids mastication of the rubber and enables high throughput without addition of peptizers. Duct tapes made from the adhesives display improved adhesion to steel, better adhesion bond strength, and enhanced seven-day clean removability from even difficult substrates such as marble or ceramic tile.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: January 24, 2023
    Assignee: SHURTAPE TECHNOLOGIES, LLC
    Inventor: Kevin Chou
  • Publication number: 20220403218
    Abstract: An acrylic adhesive formulation that can be used for various building envelope applications. The adhesive can be coated onto various substrates such as flashing, vapor permeable membranes, vapor impermeable membranes and roofing underlayment's to make them self-adhering. The adhesive can be applied in cold temperatures from 0 degrees Fahrenheit (?18 degrees Celsius) but will maintain integrity at high temperatures without sacrificing the bonding to common construction/fenestration surfaces. The adhesive can include a blend of a plasticizer and an ultra-violet (UV) curable acrylic base polymer, which can be crosslinked upon exposure to a narrow wavelength range of ultra-violet light.
    Type: Application
    Filed: September 30, 2020
    Publication date: December 22, 2022
    Inventors: Khaled EL-TAHLAWY, Kevin CHOU, Peter ELAFROS, Patrick EATON, Ameet KULKARNI, Edwin FRANCO
  • Publication number: 20210130652
    Abstract: According to one embodiment, a process for applying an adhesive material onto a barrier sheet substrate is provided. The process includes providing an adhesive material having viscosity of at least about 10,000 centipoise at 250° F. The adhesive material is applied to a multitude of cavities on a surface of a first tool with a coater unit in close proximity to the surface. The adhesive material is transferred from the surface of the first tool to the substrate supported on a surface of a second tool and pressed against the surface of the first tool.
    Type: Application
    Filed: April 30, 2018
    Publication date: May 6, 2021
    Inventors: Kevin CHOU, Patrick EATON, Khaled EL-TAHLAWY, Peter ELAFROS, William R. MYER, George STAMATOUKOS, Ed VARGAS
  • Patent number: 10852265
    Abstract: A system for voltage measurement of dielectric material in plasma includes a vacuum chamber. The system also includes an electrostatic receiver located outside of the vacuum chamber. The system also includes a conductive probe having a first terminus in contact with the dielectric material in the vacuum chamber and a second terminus in electrical communication with the electrostatic receiver. The system also includes a non-contact electrostatic voltmeter configured to measure a floating potential of the electrostatic receiver that corresponds to a dielectric potential of the dielectric material at a location in contact with the first terminus of the conductive probe.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: December 1, 2020
    Assignee: UNIVERSITY OF SOUTHERN CALIFORNIA
    Inventors: Kevin Chou, Joseph Wang
  • Publication number: 20190264074
    Abstract: A continuous process for making a pressure-sensitive adhesive is disclosed. A mixture comprising natural rubber having a Mooney viscosity of 85 to 100, a tackifier, a filler, and 0.1 to 5 wt. % of an added C12-C24 fatty acid based on the amount of mixture is masticated in a first section of a single- or twin-screw extruder. Mastication of the mixture continues in at least one subsequent extruder section in the presence of additional tackifier. The product is a homogeneous, reduced-viscosity pressure-sensitive adhesive. The minor proportion of added C12-C24 fatty acid aids mastication of the rubber and enables high throughput without addition of peptizers. Duct tapes made from the adhesives display improved adhesion to steel, better adhesion bond strength, and enhanced seven-day clean removability from even difficult substrates such as marble or ceramic tile.
    Type: Application
    Filed: May 14, 2019
    Publication date: August 29, 2019
    Inventor: Kevin Chou
  • Patent number: 10329463
    Abstract: A continuous process for making a pressure-sensitive adhesive is disclosed. A mixture comprising natural rubber having a Mooney viscosity of 85 to 100, a tackifier, a filler, and 0.1 to 5 wt. % of an added C12-C24 fatty acid based on the amount of mixture is masticated in a first section of a single- or twin-screw extruder. Mastication of the mixture continues in at least one subsequent extruder section in the presence of additional tackifier. The product is a homogeneous, reduced-viscosity pressure-sensitive adhesive. The minor proportion of added C12-C24 fatty acid aids mastication of the rubber and enables high throughput without addition of peptizers. Duct tapes made from the adhesives display improved adhesion to steel, better adhesion bond strength, and enhanced seven-day clean removability from even difficult substrates such as marble or ceramic tile.
    Type: Grant
    Filed: May 19, 2016
    Date of Patent: June 25, 2019
    Assignee: SHURTAPE TECHNOLOGIES, LLC
    Inventor: Kevin Chou
  • Publication number: 20180372666
    Abstract: A system for voltage measurement of dielectric material in plasma includes a vacuum chamber. The system also includes an electrostatic receiver located outside of the vacuum chamber. The system also includes a conductive probe having a first terminus in contact with the dielectric material in the vacuum chamber and a second terminus in electrical communication with the electrostatic receiver. The system also includes a non-contact electrostatic voltmeter configured to measure a floating potential of the electrostatic receiver that corresponds to a dielectric potential of the dielectric material at a location in contact with the first terminus of the conductive probe.
    Type: Application
    Filed: June 21, 2018
    Publication date: December 27, 2018
    Inventor: Kevin Chou
  • Publication number: 20170335148
    Abstract: A continuous process for making a pressure-sensitive adhesive is disclosed. A mixture comprising natural rubber having a Mooney viscosity of 85 to 100, a tackifier, a filler, and 0.1 to 5 wt. % of an added C12-C24 fatty acid based on the amount of mixture is masticated in a first section of a single- or twin-screw extruder. Mastication of the mixture continues in at least one subsequent extruder section in the presence of additional tackifier. The product is a homogeneous, reduced-viscosity pressure-sensitive adhesive. The minor proportion of added C12-C24 fatty acid aids mastication of the rubber and enables high throughput without addition of peptizers. Duct tapes made from the adhesives display improved adhesion to steel, better adhesion bond strength, and enhanced seven-day clean removability from even difficult substrates such as marble or ceramic tile.
    Type: Application
    Filed: May 19, 2016
    Publication date: November 23, 2017
    Inventor: Kevin Chou
  • Patent number: 9457412
    Abstract: Tungsten carbide drill bits for removing material from alloys and other hard materials are disclosed. A conventional drill bit is modified by removing material from the forward portion of the bit to increase the radius of the cutting edge. The drill bit is then coated with a nanostructured diamond film using a chemical vapor deposition process.
    Type: Grant
    Filed: December 28, 2010
    Date of Patent: October 4, 2016
    Assignee: The Board of Trustees of the University of Alabama for and on behalf of the University of Alabama
    Inventors: Yuag-Shan Kevin Chou, Raymond G. Thompson
  • Patent number: 9308623
    Abstract: A pad conditioner may include multiple independently mounted conditioning elements configured to condition a polishing pad used in, e.g., a chemical mechanical polishing (CMP) process. In some embodiments, the pad conditioner may include a main assembly disk and a main assembly base plate attached to the main assembly disk via a gimbal connection. A plurality of pad conditioner assemblies may be attached to the main assembly base plate. In some embodiments, each pad conditioner assembly may include a pad conditioner disk attached to the main assembly base plate, a pad conditioner base attached to the pad conditioner disk via a gimbal connection, and a conditioning element attached to the pad conditioner base. Methods of conditioning a polishing pad are also provided, as are other aspects.
    Type: Grant
    Filed: April 18, 2014
    Date of Patent: April 12, 2016
    Assignee: Applied Materials, Inc.
    Inventors: Hung Chen, Shou-Sung Chang, Jason Garcheung Fung, Matthew A. Gallelli, Paul D. Butterfield, Kevin Chou
  • Patent number: 8875077
    Abstract: A system, method, and computer program product for cell-aware fault model generation. Embodiments determine defects of interest for a cell, typically from cell layout and a transistor-level cell netlist. A circuit simulator performs analog fault simulation on the transistor-level netlist to determine detectable defects from the defects of interest, and detection conditions for the detectable defects. The circuit simulator employs fault sensitivity analysis (FSA) for amenable cells for greatly accelerated fault detection. Embodiments generate and output cell-aware fault models for the detectable defects from the detection conditions, for use in automated test pattern generation.
    Type: Grant
    Filed: February 10, 2014
    Date of Patent: October 28, 2014
    Assignee: Cadence Design Systems, Inc.
    Inventors: Donald J. O'Riordan, Bassilios Petrakis, Kevin Chou
  • Publication number: 20140315473
    Abstract: A pad conditioner may include multiple independently mounted conditioning elements configured to condition a polishing pad used in, e.g., a chemical mechanical polishing (CMP) process. In some embodiments, the pad conditioner may include a main assembly disk and a main assembly base plate attached to the main assembly disk via a gimbal connection. A plurality of pad conditioner assemblies may be attached to the main assembly base plate. In some embodiments, each pad conditioner assembly may include a pad conditioner disk attached to the main assembly base plate, a pad conditioner base attached to the pad conditioner disk via a gimbal connection, and a conditioning element attached to the pad conditioner base. Methods of conditioning a polishing pad are also provided, as are other aspects.
    Type: Application
    Filed: April 18, 2014
    Publication date: October 23, 2014
    Inventors: Hung Chen, Shou-Sung Chang, Jason Garcheung Fung, Matthew A. Gallelli, Paul D. Butterfield, Kevin Chou
  • Patent number: 8160858
    Abstract: A method of efficient library characterization of a circuit of a logic gate having a plurality of transistors and a plurality of nodes defining interconnection points in the circuit is disclosed. The method includes determining a plurality of vectors for a plurality of arcs. Each of the plurality of vectors represents possible data bits to inputs and nodes of the logic gate. The method performs circuit pruning for each of distinct vectors. The circuit pruning includes identifying an active circuit for each vector. Then, the circuit simulations limited to a plurality of transistors in the active circuit are performed. The circuit pruning and circuit simulations are repeated for remaining ones of the plurality of substantially distinct vectors. The results of the circuit simulations are then stored on a non-volatile compute readable media, for each active circuit corresponding to each of the plurality of substantially distinct vectors.
    Type: Grant
    Filed: December 16, 2010
    Date of Patent: April 17, 2012
    Assignee: Cadence Design Systems, Inc.
    Inventors: Ken Tseng, Kevin Chou
  • Patent number: 7937256
    Abstract: A method of efficient library characterization of a circuit of a logic gate having a plurality of transistors and a plurality of nodes defining interconnection points in the circuit is disclosed. The method includes determining a plurality of vectors for a plurality of arcs. Each of the plurality of vectors represents possible data bits to inputs and nodes of the logic gate. The method selects a plurality of substantially distinct vectors from the plurality of vectors for each of the plurality of arcs, and performs circuit pruning for each of the plurality of substantially distinct vectors, taking each one substantially distinct vector at a time. The circuit pruning includes identifying an active circuit for each vector. The active circuit is identified by determining which circuit features are activated when applying a particular one of the substantially distinct vectors. Then, the circuit simulations limited to a plurality of transistors in the active circuit are performed.
    Type: Grant
    Filed: November 20, 2007
    Date of Patent: May 3, 2011
    Assignee: Altos Design Automation, Inc.
    Inventors: Ken Tseng, Kevin Chou
  • Publication number: 20110087478
    Abstract: A method of efficient library characterization of a circuit of a logic gate having a plurality of transistors and a plurality of nodes defining interconnection points in the circuit is disclosed. The method includes determining a plurality of vectors for a plurality of arcs. Each of the plurality of vectors represents possible data bits to inputs and nodes of the logic gate. The method selects a plurality of substantially distinct vectors from the plurality of vectors for each of the plurality of arcs, and performs circuit pruning for each of the plurality of substantially distinct vectors, taking each one substantially distinct vector at a time. The circuit pruning includes identifying an active circuit for each vector. The active circuit is identified by determining which circuit features are activated when applying a particular one of the substantially distinct vectors. Then, the circuit simulations limited to a plurality of transistors in the active circuit are performed.
    Type: Application
    Filed: December 16, 2010
    Publication date: April 14, 2011
    Applicant: Altos Design Automation, Inc.
    Inventors: Ken Tseng, Kevin Chou
  • Publication number: 20080133202
    Abstract: A method of efficient library characterization of a circuit of a logic gate having a plurality of transistors and a plurality of nodes defining interconnection points in the circuit is disclosed. The method includes determining a plurality of vectors for a plurality of arcs. Each of the plurality of vectors represents possible data bits to inputs and nodes of the logic gate. The method selects a plurality of substantially distinct vectors from the plurality of vectors for each of the plurality of arcs, and performs circuit pruning for each of the plurality of substantially distinct vectors, taking each one substantially distinct vector at a time. The circuit pruning includes identifying an active circuit for each vector. The active circuit is identified by determining which circuit features are activated when applying a particular one of the substantially distinct vectors. Then, the circuit simulations limited to a plurality of transistors in the active circuit are performed.
    Type: Application
    Filed: November 20, 2007
    Publication date: June 5, 2008
    Applicant: Altos Design Automation, Inc.
    Inventors: Ken Tseng, Kevin Chou
  • Publication number: 20070090577
    Abstract: A method for producing a ceramic article comprising the steps of providing a plasticized ceramic precursor batch composition comprising an inorganic ceramic powder batch composition; a liquid vehicle; and an organic binder system comprising at least one organic lubricant grafted to a cellulose ether binder. An extruded green body can be formed from the plasticized ceramic precursor batch composition and subsequently fired under conditions effective to convert the extruded green body into a unitary ceramic article. Also provided are ceramic articles manufactured by the methods disclosed herein.
    Type: Application
    Filed: October 20, 2005
    Publication date: April 26, 2007
    Inventor: Kevin Chou
  • Publication number: 20060272800
    Abstract: A radiator fan shroud (100) is disclosed that is adapted to be attached to a vehicle radiator (96)—for example, the radiator of a Class 8 truck. The fan shroud includes a peripheral cover portion (112) and a ring assembly (102) that encloses the blades of the engine-driven radiator fan (88). The ring assembly may be formed integrally with the peripheral cover portion or may include a separable ring extension (120). The ring assembly includes a plurality of ports (104) defined by vanes (106) at the rearward portion of the ring assembly. The ports are selectively positioned to manage the airflow in the engine compartment, directing the airflow towards selected locations. The vanes may be fluted. The fan shroud may be formed from two or more pieces that cooperatively form the fan shroud, to facilitate installation and maintenance of the fan shroud.
    Type: Application
    Filed: June 2, 2005
    Publication date: December 7, 2006
    Applicant: PACCAR Inc
    Inventors: Alec Wong, Dan Farmer, Brian Campbell, Adam Hailey, Kevin Chou, Tim Schick
  • Patent number: 6120322
    Abstract: A memory card connection device includes an upper card connector stacked on a lower card connector. The card connectors have a rear connector section from which two guide racks extend toward a front card receiving port thereby defining therebetween a first space sufficient for accommodating a type I or type II memory card. A single cover plate is positioned on and fixed to the upper card connector. The cover plate has a low level section directly fixed to the rear connector section of the upper card connector and a high level section positioned above the guide racks and connected to the low level section by a riser panel thereby forming a step-like configuration. The high level section of the cover plate is distant from the upper card connector thereby defining a second space therebetween in communication with the first space of the upper card connector thereby defining an enlarged overall space for receiving a type III memory card without interfering with the lower card connector.
    Type: Grant
    Filed: April 13, 1999
    Date of Patent: September 19, 2000
    Assignee: Hon Hai Precision Ind. Co., Ltd.
    Inventors: Yu-Ming Ho, Kevin Chou
  • Patent number: D732184
    Type: Grant
    Filed: December 5, 2013
    Date of Patent: June 16, 2015
    Inventor: Kevin Chou