Patents by Inventor Kevin C. K. Lin

Kevin C. K. Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8671247
    Abstract: An L2 cache, method and computer program product for transferring an inbound bus operation to a processor side handling machine. The method includes a bus operation handling machine accepting the inbound bus operation received over a system interconnect, the bus operation handling machine identifying a demand operation of the processor side handling machine that will complete the bus operation, the bus operation handling machine sending the identified demand operation to the processor side handling machine, and the processor side handling machine performing the identified demand operation.
    Type: Grant
    Filed: December 14, 2010
    Date of Patent: March 11, 2014
    Assignee: International Business Machines Corporation
    Inventors: Jason A. Cox, Kevin C K Lin, Eric F. Robinson, Mark J. Wolski
  • Patent number: 8639889
    Abstract: One embodiment provides a cached memory system including a memory cache and a plurality of read-claim (RC) machines configured for performing read and write operations dispatched from a processor. According to control logic provided with the cached memory system, a hazard is detected between first and second read or write operations being handled by first and second RC machines. The second RC machine is suspended and a subset of the address bits of the second operation at specific bit positions are recorded. The subset of address bits of the first operation at the specific bit positions are broadcast in response to the first operation being completed. The second operation is then re-requested.
    Type: Grant
    Filed: January 31, 2011
    Date of Patent: January 28, 2014
    Assignee: International Business Machines Corporation
    Inventors: Jason A. Cox, Robert J. Dorsey, Kevin C K Lin, Eric F. Robinson
  • Patent number: 7752393
    Abstract: A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design for forwarding store data to loads in a pipelined processor is provided. In one implementation, a processor is provided that includes a decoder operable to decode an instruction, and a plurality of execution units operable to respectively execute a decoded instruction from the decoder. The plurality of execution units include a load/store execution unit operable to execute decoded load instructions and decoded store instructions and generate corresponding load memory operations and store memory operations. The store queue is operable to buffer one or more store memory operations prior to the one or more memory operations being completed, and the store queue is operable to forward store data of the one or more store memory operations buffered in the store queue to a load memory operation on a byte-by-byte basis.
    Type: Grant
    Filed: May 4, 2008
    Date of Patent: July 6, 2010
    Assignee: International Business Machines Corporation
    Inventors: Jason A. Cox, Kevin C. K. Lin, Eric F. Robinson