Abstract: Disclosure in this specification is of a greyhound lure support carrier engageable with a support track is located about a greyhound racing track. The support carrier is engageable and disengageable from the track in one example, the carrier housing supports multiple wheels some of which are in constant contact with the track to drive the carrier housing along the track and other wheels are free-wheeling guides along the track and to ensure the carrier housing stays on the track. The support carrier comprises a chassis accommodating, a battery to supply electric power; an electric motor having an axle, the electric motor operatively connected to the battery, and to drive the rotation of an axle; a rotatable friction arrangement connected to a driven axle and located so as to frictionally engage with the support track. There is a suspension arrangement moveable against a portion of the support track to permit suspension of the chassis from the support track.

Abstract: The invention presents techniques for making the operation of an automated external defibrillator easier to understand for an operator. The automated external defibrillator includes defibrillation electrodes packaged in a sealed, easy-to-open pouch. Visual cues such as instructive pictures show the operator how to open the pouch, retrieve the defibrillation electrodes and correctly position the electrodes on a patient's chest.

Abstract: The invention presents techniques for making the operation of an automated external defibrillator easier to understand for an operator. The automated external defibrillator includes defibrillation electrodes packaged in a sealed, easy-to-open pouch. Visual cues such as instructive pictures show the operator how to open the pouch, retrieve the defibrillation electrodes and correctly position the electrodes on a patient's chest.

Abstract: Methods and apparatus are provided for a limited use ECG electrode set. The electrode set includes a plurality of limited use electrodes capable of being affixed to a human patient so as to receive patient information from the patient such as ECG data. Cables are also affixed to each electrode, and each cable is capable of transmitting patient information therethrough. A connector is affixed to each cable, and the connector is likewise capable of transmitting patient information. A sealing wedge may be molded around each cable forming a seal therebetween. The electrode set may be disposed at least partially in a packaging interior region, and the packaging may be hermetically sealed. Further the packaging may be sealed around the sealing wedge in forming the hermetic seal. The limited use electrode set may be opened and deployed from its packaging in situations that call for receiving patient data such as ECG information.

Abstract: The invention presents an apparatus and techniques for determining whether a medical electrode, such as a defibrillation electrode coupled to an automated external defibrillator, is in a condition for replacement. The determination can be made as a function of one or more data. In one exemplary embodiment, the determination is a function of one or more measurements of an impedance of a hydrogel bridge in a test module. In another exemplary embodiment, the determination is a function of one or more environmental condition data from one or more environmental sensors.

Abstract: A multiplexor has two data inputs and three control inputs. The multiplexor is realized using two stages of three-state inverters coupled by a logic gate so as to provide a compact layout and high speed drive capability.

Abstract: A multiply/accumulate unit utilizes a fully static 32-bit arithmetic logic unit with two stage carry bypass. A four transistor carry chain places minimal loading on the chain.

Abstract: An arithmetic unit for multiplying and accumulating signed binary data and indicating an occurrence of a signed arithmetic overflow includes a multiplier-accumulator and an overflow flag register. The multiplier-accumulator receives and selectively multiples and accumulates signed binary data, and provides output data representing the multiplied and accumulated data and a sign bit representing its polarity, i.e. positive or negative. The flag register provides two "sticky" flag bits for indicating whether a signed arithmetic overflow (positive or negative) of the multiplied and accumulated data has occurred. The flag bits are "sticky" in that once a flag has been set, it cannot be reset by another arithmetic overflow condition. Instead, it must be specifically reset. The sign bit is used to selectively set one of the two sticky flag bits to a true state to indicate the direction (positive or negative) of the first arithmetic overflow.

Abstract: An integrated circuit (IC) processor architecture is disclosed that implements hardware, signal processing (DSP) functions with less digital improved speed and a more efficient layout. The resources of the central processing unit (CPU) are used in conjunction with an integrated multiply/accumulate unit to perform DSP operations. Internal registers of the CPU are used to store pointers which reference a circular sample buffer. The CPU thus manages the selection and transfer of coefficients from the sample buffer to the multiply/accumulate unit, thereby allowing a minimum amount of lower speed hardware to be used for the multiply/accumulate unit and permitting DSP operations to be performed in parallel with CPU operations.

Abstract: The present invention provides a structured integrated circuit design methodology. The methodology is based on describing a two-phase logic function using a high level behavioral description flow chart, properly sizing devices to be used in the circuit for speed and reducing trial and error in circuit layout implementation using novel chip planning techniques. The methodology begins with the definition of signal types based on the circuit function that creates a particular signal and the type of input signal that feeds the circuit function. A rigid set of rules is then established for use of the signal types. Next the technical specification of the two-phase logic function is defined and utilized to create a behavioral flow chart using defined symbols. An associated database of corresponding Boolean equations is then created that defines the parameters of the various elements of the flow chart.

Abstract: An integrated circuit processor architecture that implements digital signal processing (DSP) functions with less hardware, improved speed and a more efficient layout. The central processing unit (CPU) resources are used in conjunction with an integrated multiply/accumulate unit to perform DSP operations. Use of the CPU's internal register for the circular buffer of the DSP multiply/accumulate function allows a minimum amount of lower speed hardware to be used for the multiply/accumulate unit and permits DSP operations to be performed in parallel. The multiply/accumulate unit takes advantage of the inherent accumulating properties of conventional multiplier designs to perform multiplication of two signed binary numbers using the modified Booth's algorithm but in both reduced cycle time and hardware requirements. This is accomplished by using the adder within the multiplier to sum the product terms.