Abstract: An automatic profiling system and method determines an algorithm profile including performance predictability and pricing of a parallel processing algorithm.

Abstract: A method for generating a decomposition graph having an effective cyclomatic complexity measure below the McCabe limit for a decomposition level, includes the steps of determining the number of processes and/or objects within the decomposition level, determining a cyclomatic complexity measure based on the number of processes and/or objects within the decomposition level, determining a number of dimensions required to display the decomposition level such that the cyclomatic complexity does not exceed the McCabe limit, and generating the decomposition graph based on the determined number of dimensions required to display the decomposition level.

Abstract: A system and method for detecting decomposition errors in a parallel processing software design having at least two decomposition levels, where each decomposition level has at least one process. The system and method further identifies improper control flow, looping structure and/or dataflow within the software design and restructures the software design to remove any improper elements.

Abstract: A system and method for generating a specific level of software testing of algorithms and applications. A test plan, including input parameter values, expected output parameter values, and dataset size, is entered. The test plan is then executed, and results of the test are scored in accordance with predetermined software testing level definitions, yielding one of a predetermined possible testing levels achieved by the tested software.

Abstract: A system and method for raising funds for the development of a software application by pre-licensing a software application in a parallel processing development environment. Further including a pre-license auction aspect for auctioning off excess application uses to other users that exist within the development environment.

Abstract: A résumé of a developer working with a parallel processing development environment is, at least in part, automatically generated by the parallel processing development environment based upon information of the developers work experience within the development environment.

Abstract: Parallel Processing Communication Accelerator (PPCA) systems and methods for enhancing performance of a Parallel Processing Environment (PPE). In an embodiment, a Message Passing Interface (MPI) devolver enabled PPCA is in communication with the PPE and a host node. The host node executes at least a parallel processing application and an MPI process. The MPI devolver communicates with the MPI process and the PPE to improve the performance of the PPE by offloading MPI process functionality to the PPCA. Offloading MPI processing to the PPCA frees the host node for other processing tasks, for example, executing the parallel processing application, thereby improving the performance of the PPE.

Abstract: A computer-implemented method for identifying a new software application to be developed. A computer database is searched for matching keywords that correspond to any of a group of selected keywords, indicative of the new application. The database contains descriptive keywords which are indicative of a set of existing applications. If no matching keywords are found in the database, then a description of the new application is requested from the potential user; the description of the new application is received from the potential user; and the description of the new application is used as a basis for developing the new application.

Abstract: A system and method for automatic code-design and file/database-design association. Existing source code is analyzed for process and control elements. The control elements are encapsulated as augmented state machines and the process elements are encapsulated as kernels. The new elements can then have meta-data attached (including, a name, I/O method, and test procedures), allowing software code sharing and automatic code/file/database upgrading, as well as allowing sub-subroutine level code blocks to be accessed directly.

Abstract: A system and method for performing functional decomposition of a software design to generate a computer-executable finite state machine. Initially, the software design is received in a form wherein functions in the software design are repetitively decomposed into (1) data and control transformations. Included between the functions are control flow indicators which have transformation-selection conditions associated therewith. The data transformations and the control transformations are translated into states in the finite state machine. The transformation-selection conditions associated with the control transformations are translated into state transitions in the finite state machine.

Abstract: Parallel Processing Communication Accelerator (PPCA) systems and methods for enhancing performance of a Parallel Processing Environment (PPE). In an embodiment, a Message Passing Interface (MPI) devolver enabled PPCA is in communication with the PPE and a host node. The host node executes at least a parallel processing application and an MPI process. The MPI devolver communicates with the MPI process and the PPE to improve the performance of the PPE by offloading MPI process functionality to the PPCA. Offloading MPI processing to the PPCA frees the host node for other processing tasks, for example, executing the parallel processing application, thereby improving the performance of the PPE.

Abstract: A method for parallelization of an algorithm executing on a parallel processing system. An extension element is generated for each of the sections of the algorithm, where the sections comprise: distribution of data to multiple processing elements, transfer of data from outside of the algorithm to inside of the algorithm, global cross-communication of data between processing elements, moving data to a subset of the processing elements, and transfer of data from inside of the algorithm to outside of the algorithm. Each extension element functions to provide parallelization at a respective place in the algorithm where parallelization of the algorithm may occur.

Abstract: A method for interconnecting multiple computational devices in a parallel computing network including a plurality of serially associated pairs of nodes, wherein each of the pairs of nodes is interconnected via at least one physical communication channel. A sufficient virtual channel rate required to provide a predetermined amount of Amdahl scaling is first determined. The maximum number of virtual channels, each having a transmission rate at least equal to the sufficient virtual channel rate, that can be implemented over each physical communication channel is then determined. The physical communication channel between each of the nodes is then subdivided into the determined maximum number of virtual channels.

Abstract: A parallel processing development environment has a graphical process control server that provides an interface through which a developer may access the environment to create a parallel processing routine. The development environment also includes a financial server for managing license and usage fees for the parallel processing routine, wherein the developer of the parallel processing routine receives a portion of the license and usage fees received for the routine. The environment identifies plagiarism and malicious software within the parallel processing routine.

Abstract: We discuss a software design and automatic coding system particularly applicable to generating code for massively parallel computing systems. This system operates on a high performance computer and provides a collaborative, interactive, iterative method of defining and designing software for parallel computing systems, and generates software code directly from design elements without the use of code patterns, meta-data, or domain rules, reducing bugs and cost while retaining the time-to-market advantages of iterative ad-hoc methods.

Abstract: A computer-implemented method for identifying a new software application to be developed. A computer database is searched for matching keywords that correspond to any of a group of selected keywords, indicative of the new application. The database contains descriptive keywords which are indicative of a set of existing applications. If no matching keywords are found in the database, then a description of the new application is requested from the potential user; the description of the new application is received from the potential user; and the description of the new application is used as a basis for developing the new application.

Abstract: Systems and methods form and control a supercomputer based upon a parallel processing architecture such as a Howard cascade. A graphical user interface allows a user to interact with one or more virtual power centers of the supercomputer facility. A plurality of processing nodes self-organize into one or more virtual power centers. The processing nodes utilize overlapped input and output for improved communication.

Abstract: A method using for performing a scatter-type data distribution among a cluster of computational devices. A number of nodes (equal to a value Cg, the number of tree generator channels) are initially generated, each connected to an initial generator, to create respective initial root nodes of an initial tree structure. Data is transmitted from the initial generator to each of the initial root nodes. Cg root nodes, each connected to a respective new generator, are generated to create respective roots of Cg newly generated tree structures. Each of the tree structures is expanded by generating Ct (the number of communication channels per node in each tree structure) new nodes connected to each node generated in each previous step. Data is then transmitted to each of the new nodes from an immediately preceding one of the nodes, and from each new generator to an associated root node.

Abstract: A multiprocessor system on a chip (MPSoC) implements parallel processing and include a plurality of cores with inter-core communication. This communication is implemented by an on-chip switch fabric in communication with each core, or by shared memory in communication with each core. In another embodiment, a parallel processing system is implemented as a Howard Cascade and uses shared memory for implementing inter-chip communication.

Abstract: A parallel processing computer is described that has several processing devices of several different processing device types each communicating over a computer network. The computer has at least one conversion device in communication with the processing devices, the conversion device being a processing device having conversion code for translating at least some task allocation and other messages from a format understood by the conversion device into a format understood for execution by a particular type of the several types of the processing devices. The computer also has at least one access device in communication with the at least one conversion device, the access device having program code for allocating tasks to processing devices and generating task allocation messages to processing devices. The computer network in an embodiment involves portions of the cellular telephone network as well as part of the internet.