Abstract: Methods and apparatuses are described for determining mask layouts for printing a design intent on a wafer using a spacer-is-dielectric self-aligned double-patterning process. A system can determine whether a graph corresponding to a design intent is two-colorable. If the graph is not two-colorable, the system can merge one or more pairs of shapes in the design intent to obtain a modified design intent, so that a modified graph corresponding to the modified design intent is two-colorable. The system can then determine a two-coloring for the modified graph. Next, the system can place one or more core shapes in a mandrel mask layout which correspond to vertices in the modified graph that are associated with a selected color in the two-coloring. The system can then place one or more shapes in a trim mask layout for separating the shapes in the design intent that were merged.

Abstract: Methods and apparatuses are described for determining mask layouts for printing a design intent on a wafer using a spacer-is-dielectric self-aligned double-patterning process. A system can determine whether a graph corresponding to a design intent is two-colorable. If the graph is not two-colorable, the system can merge one or more pairs of shapes in the design intent to obtain a modified design intent, so that a modified graph corresponding to the modified design intent is two-colorable. The system can then determine a two-coloring for the modified graph. Next, the system can place one or more core shapes in a mandrel mask layout which correspond to vertices in the modified graph that are associated with a selected color in the two-coloring. The system can then place one or more shapes in a trim mask layout for separating the shapes in the design intent that were merged.

Abstract: One embodiment of the present invention provides a system that accurately models polarization effects in an optical lithography system for manufacturing integrated circuits. During operation, the system starts by receiving a polarization-description grid map for a lens pupil in the optical lithography system. The system then constructs a pupil-polarization model by defining a vectorial matrix at each grid point in the grid map, wherein the vectorial matrix specifies a pupil-induced polarization effect on an incoming optical field at the grid point. Next, the system enhances a lithography model for the optical lithography system by incorporating the pupil-polarization model into the lithography/OPC model. The system then uses the enhanced lithography model to perform convolutions with circuit patterns on a mask in order to simulate optical lithography pattern printing.

Abstract: A method is provided for making an integrated circuit. Cell representing a layout of a set of features, is divided into at least a first region and a second region. Optical Proximity Correction is carried out on at least the first region of cell. One or more instances of cell are located to define IC prior to carrying out final OPC optimisation on the second regions of each cell in the defined IC.

Abstract: A method for improving manufacturability of a design includes performing space or enclosure checks on multiple interacting layers of a layout design and then using the resulting space or enclosure data to move predetermined feature edges in an altered design database to decrease the risk of features widths, feature spaces or feature enclosures being patterned smaller than designed. In some embodiments, the upsized features are larger in the wafer circuit pattern than are drawn in a designed database. The method for improving manufacturability of a design, in some embodiments, is stored on a computer readable storage medium.

Abstract: Photoresist on a wafer is exposed using tiles on a mask that improve flare performance. Features that are not to be exposed on the photoresist correspond to features on the mask. The various features are surrounded by other features that vary and thus affect flare differently. Selected features have tiles added nearby but also far enough away to improve uniformity in the effects of flare on the various features that are intended to be present in the photoresist. The tiles are made either very small in width or partially absorbing so that the tiles are not resolved in the photoresist. Thus the tiles reduce flare but do not alter the desired pattern in the photoresist.

Abstract: A process for forming a semiconductor structure includes forming a gate dielectric overlying a substrate, a conductive gate electrode overlying the gate dielectric, a barrier layer overlying and in physical contact with the conductive gate electrode, and an organic anti-reflective coating (ARC) layer overlying and in physical contact with the barrier layer.

Abstract: A method of designing and forming a reticle (404), as well as the manufacture of a semiconductor substrate (410) using the reticle, includes defining a first edge of a reticle layout file. The first edge corresponds to a reference feature (12,14). The method further includes using the reference feature to insert a subresolution assist feature (62,64) into the reticle layout file. The subresolution assist feature is at an angle (&thgr;) with respect to a line (82,84) containing the first edge, wherein the angle differs from 90 degrees. In one embodiment, the subresolution assist features can be manually or automatically inserted into the layout file after the locations of the assist features have been determined. The subresolution assist features are not patterned on the substrate, but assist in forming resist features of uniform dimension.

Abstract: A method of generating a design of a reticle for a photolithography process. The reticle may include phase shift features, binary features, and mixed features. The method includes generating a reticle design from a pattern layout and then optimizing the reticle design. In some examples, generating the reticle design includes binning the features of the layout based on feature width. Examples of optimization operations include an over/under operation, an under/over operation, a feature segment expansion operation, a feature edge portion conversation from a binary portion to a phase shift portion, a corner binary segment expansion, a discontinuity removal operation, and a feature dimension change operation that includes a determination of a Mask Error Factor (MEF).

Abstract: Photoresist on a wafer is exposed using tiles on a mask that improve flare performance. Features that are not to be exposed on the photoresist correspond to features on the mask. The various features are surrounded by other features that vary and thus affect flare differently. Selected features have tiles added nearby but also far enough away to improve uniformity in the effects of flare on the various features that are intended to be present in the photoresist. The tiles are made either very small in width or partially absorbing so that the tiles are not resolved in the photoresist. Thus the tiles reduce flare but do not alter the desired pattern in the photoresist.

Abstract: A method (10) for correcting lithography error includes generating (18) data that defines relationships between at least one predetermined design layout parameter and a known minimum required lithographic process capability (e.g. minimum feature spacing), and then using the data to upsize (30) predetermined isolated features or portions of predetermined isolated or semi-isolated features. In some embodiments, the resulting wafer circuit pattern (70) has isolated features (71, 72, 74) that are all larger than a predetermined minimum width. The upsized features are larger in the wafer circuit pattern (70) than they are drawn in a designed database. The method for correcting the lithography error, in some embodiments, is stored on a computer readable storage medium.

Abstract: A method (10) for correcting lithography error includes generating (18) data that defines relationships between at least one predetermined design layout parameter and a known minimum required lithographic process capability (e.g. minimum feature spacing), and then using the data to upsize (30) predetermined isolated features or portions of predetermined isolated or semi-isolated features. In some embodiments, the resulting wafer circuit pattern (70) has isolated features (71, 72, 74) that are all larger than a predetermined minimum width. The upsized features are larger in the wafer circuit pattern (70) than they are drawn in a designed database. The method for correcting the lithography error, in some embodiments, is stored on a computer readable storage medium.

Abstract: A lithographic reticle with subresolution features in the design-pattern is used to control critical dimensions in a semiconductor manufacturing process. After the location of design and processing features is determined, subresolution features are formed in areas devoid of design and processing features. The subresolution features can substantially fill all of the area devoid of design processing features or, instead, selectively fill portions of the area. In one embodiment, the width of the area devoid of design and processing features is less than two times the width of a feature. The presence of the subresolution features results in improved control of small dimensions of features in semiconductor processing, thereby increasing yield and device performance.

Abstract: A lithographic reticle with subresolution features in the design-pattern is used to control critical dimensions in a semiconductor manufacturing process. To determine the location of subresolution features the location of design and processing features is determined and the subresolution features are formed in areas devoid of design and processing features. The subresolution features can substantially fill all of the area devoid of design and processing features or, instead, selectively fill portions of the area. In one embodiment, the width of the area devoid of design and processing features is less than two times the width of a feature. The presence of the subresolution features results in improved control of small dimensions of features in semiconductor processing, thereby increasing yield and device performance.

Abstract: A hardmask layer (34) is formed over insulating layers (26, 24, 22 and 20), and an antireflective layer (36) is formed overlying the hardmask layer (34). A resist layer (38) is formed overlying the antireflective layer (36), and an opening is formed in the resist layer to expose a surface portion of the antireflective layer (36). The exposed surface portion of the antireflective layer (36) and portions of the hardmask layer (34) are etched to expose a surface portion of the insulating layers (26, 24, 22 and 20), and a feature opening (61) is formed in the insulating layers (26, 24, 22 and 20). A conductive material (74) is deposited to fill the feature opening (61), and portions of the conductive material (74) lying outside the opening are removed.

Abstract: Integrated circuit designs are continually shrinking in size. Lithographic processes are used to transfer these designs to a semiconductor substrate. These processes typically require that the exposure wavelength of light be shorter than the smallest dimension of the elements within the circuit design. When this is not the case, exposure energy such as light behaves more like a wave than a particle. Additionally, mask manufacturing, photoresist chemical diffusion, and etch effects cause pattern transfer distortions. The result is that circuit elements do not print as designed. To counter this effect the circuit designs themselves can be altered so that the final printed results better matches the initial desired design. The process of altering designs in this way is called Lithographic Proximity Correction (LPC). Square (142), cross (162), octagon (172), and hammerhead (202) serifs are added to integrated circuit designs by shape manipulation functions to perform two dimensional (2-D) LPC.

Abstract: Integrated circuit designs are continually shrinking in size. Lithographic processes are used to pattern these designs onto a semiconductor substrate. These processes typically require that the wavelength of exposure used during printing be significantly shorter than the smallest dimension of the elements within the circuit design. When this is not the case, the exposure radiation behaves more like a wave than a particle. Additionally, mask manufacturing, photoresist chemical diffusion and etch effects cause pattern transfer distortions. The result is that circuit elements do not print as designed. To counter this effect the designs themselves can be altered so that the final printed results better match the initial desired design. The process of altering designs in this way is called Lithographic Proximity Correction (LPC). Edge assist shapes and edge biasing features are added to integrated circuit designs by shape manipulation functions to perform one dimensional (1-D) LPC.

Abstract: A process for fabricating a semiconductor device includes the formation of a lithographic reticle (20) having a lithographic pattern (18) overlying a reticle substrate (10). In one embodiment, a reticle inspection database incorporates altered resolution assisting features (30,32) to inspect the lithographic pattern (18). The dimensional difference between the reticle inspection database and the lithographic reticle is substantially equal to the process bias realized during reticle fabrication. Inspection of the lithographic reticle (20) using a reticle inspection database containing altered resolution assisting features reduces the false detection of defects and provides increased sensitivity in the reticle inspection process.