Patents by Inventor Kevin Dean Lucas

Kevin Dean Lucas has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Stochastic-aware lithographic models for mask synthesis
    Patent number: 11900042
    Abstract: In some aspects, a mask pattern is accessed. The mask pattern is for use in a lithography process that prints a pattern on a wafer. The mask pattern is applied as input to a deterministic model of the lithography process to predict a characteristic of the printed pattern. The deterministic model is deterministic, but it accounts for local stochastic variations of the characteristic in the printed pattern.
    Type: Grant
    Filed: November 9, 2021
    Date of Patent: February 13, 2024
    Assignee: Synopsys, Inc.
    Inventors: Kevin Dean Lucas, Yudhishthir Prasad Kandel, Ulrich Welling, Ulrich Karl Klostermann, Zachary Adam Levinson
  • STOCHASTIC-AWARE LITHOGRAPHIC MODELS FOR MASK SYNTHESIS
    Publication number: 20220146945
    Abstract: In some aspects, a mask pattern is accessed. The mask pattern is for use in a lithography process that prints a pattern on a wafer. The mask pattern is applied as input to a deterministic model of the lithography process to predict a characteristic of the printed pattern. The deterministic model is deterministic, but it accounts for local stochastic variations of the characteristic in the printed pattern.
    Type: Application
    Filed: November 9, 2021
    Publication date: May 12, 2022
    Inventors: Kevin Dean Lucas, Yudhishthir Prasad Kandel, Ulrich Welling, Ulrich Karl Klostermann, Zachary Adam Levinson
  • Method and apparatus for designing an integrated circuit using inverse lithography technology
    Patent number: 8370773
    Abstract: Method and apparatus for designing an integrated circuit by calculating an optimised reticle layout design from an IC layout design and a model describing an optical system for transferring the IC layout design onto a semiconductor wafer using a reticle, wherein the IC layout design comprises features defined by a plurality of boundaries. Approximating the plurality of boundaries to generate an approximated IC layout design suitable for the manufacture of the IC. Performing OPC simulation on at least a portion of the approximated IC layout design.
    Type: Grant
    Filed: August 16, 2006
    Date of Patent: February 5, 2013
    Assignees: Freescale Semiconductor, Inc., Koninklijke Philips Electronics N.V.
    Inventors: Kevin Dean Lucas, Robert Elliott Boone, Yves Rody
  • Method and apparatus for designing and integrated circuit
    Patent number: 8175737
    Abstract: Method and apparatus for designing an integrated circuit by adding a plurality of control points to an integrated circuit wafer design. Each control point has at least one attribute. Then, an integrated circuit wafer is manufactured using the integrated circuit wafer design. A defect on the integrated circuit wafer is then located. The control points are adjusted such that they correspond with the defect.
    Type: Grant
    Filed: July 19, 2006
    Date of Patent: May 8, 2012
    Assignees: Freescale Semiconductor, Inc., Koninklijke Philips Electronics N.V.
    Inventors: Kevin Dean Lucas, Robert Elliott Boone, James Edward Vasek, William Louis Wilkinson, Christophe Couderc
  • METHOD AND APPARATUS FOR DESIGNING AN INTEGRATED CIRCUIT
    Publication number: 20100333048
    Abstract: Method and apparatus for designing an integrated circuit by calculating an optimised reticle layout design from an IC layout design and a model describing an optical system for transferring the IC layout design onto a semiconductor wafer using a reticle, wherein the IC layout design comprises features defined by a plurality of boundaries. Approximating the plurality of boundaries to generate an approximated IC layout design suitable for the manufacture of the IC. Performing OPC simulation on at least a portion of the approximated IC layout design.
    Type: Application
    Filed: August 16, 2006
    Publication date: December 30, 2010
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Kevin Dean Lucas, Robert Elliott Boone, Yves Rody
  • METHOD AND APPARATUS FOR DESIGNING AND INTEGRATED CIRCUIT
    Publication number: 20090240364
    Abstract: Method and apparatus for designing an integrated circuit by adding a plurality of control points to an integrated circuit wafer design. Each control point has at least one attribute. Then, an integrated circuit wafer is manufactured using the integrated circuit wafer design. A defect on the integrated circuit wafer is then located. The control points are adjusted such that they correspond with the defect.
    Type: Application
    Filed: July 19, 2006
    Publication date: September 24, 2009
    Inventors: Kevin Dean Lucas, Robert Elliott Boone, James Edward Vasek, William Louis Wilkinson, Christophe Couderc