Abstract: A structured membrane fabrication method begins with a membrane wafer on a substrate and at least one thin-film on the membrane wafer such that portions of the membrane wafer are exposed. The exposed portions of the membrane wafer and each thin-film are covered with an acetone-inert protectant. Portions of the protectant are etched through to the membrane wafer while each thin-film remains fully covered by the protectant. A handle is coupled to the protectant with a wax that dissolves in acetone. Portions of the substrate are then removed to define and expose a contiguous region of the membrane wafer adjacent to each thin-film and the portions of the protectant so-etched. The wax is exposed to acetone so that it dissolves. The contiguous region of the membrane wafer is then etched through at the portions of the protectant so-etched. The protectant is then removed.

Abstract: The present invention relates to a plurality of phononic devices and a method of manufacturing thereof. In one embodiment, highly sensitive superconducting cryogenic detectors integrate phononic crystals into their architecture. The phononic structures are designed to reduce the loss of athermal phonons, resulting in lower noise and higher sensitivity detectors. This fabrication process increases the qp generation recombination rate, thus, reducing the noise equivalent power (NEP) without sacrificing the scalability. A plurality of phononic devices, such as a kinetic inductance detector (KID), a transition edge sensor (TES) bolometer, and quarterwave backshort, can be manufactured according to the methods of the present invention.

Abstract: The present invention relates to an integrated reflective backshort fabricated with a phononic-isolated kinetic inductance detector or transition edge sensor. The integrated backshort includes: a silicon wafer; a reflective metal layer bonded to the silicon wafer; a silicon first layer disposed on the reflective metal layer; a structural second layer disposed on the first layer; a first superconductor layer disposed on the second layer as a kinetic inductance detector; and a second superconductor layer disposed on the second layer as leads, a microstrip, a capacitor or filter; wherein a phononic structure is etched in the second layer, leaving holes in the second layer; and wherein the etching penetrates through the holes into the second layer, and stopping on the reflective metal layer, leaving a space under the second layer where edges of the first layer etched under the second layer define a length of the integrated backshort.

Abstract: The present invention provides a phenothiazine derivative of formula (I) for use in preventing and/or treating infection caused by bacteria carrying Type IV pili, such as N. meningitidis, and more specifically for use in preventing and/or treating meningitis. The present invention further relates to a composition for the use in preventing and/or treating infection caused by bacteria carrying Type IV pili, such as purpura fulminans and meningitis, comprising a phenothiazine derivative of formula (I) and an antibiotic selected from the group consisting of beta-lactams and aminoglycosides, and/or dexamethasone.

Abstract: The present invention provides aphenothiazine derivative for use in preventing and/or treating infectious purpura or purpura fulminans, wherein infection is caused by a bacterium. The present invention further relates to a composition for the use in preventing and/or treating infectious purpura or purpura fulminans comprising a phenothiazine derivative and an antibiotic selected in the group consisting of beta-lactams, aminoglycosides or dexamethasone.

Abstract: A thin-film transistor includes a gate electrode having a first gate electrode edge and a second gate electrode edge opposite the first gate electrode edge. The TFT also includes a drain electrode having a first drain electrode edge that overlaps the first gate electrode edge, and a second drain electrode edge that overlaps the second gate electrode edge. A method for fabricating a diode array for use in a display includes deposition of a conductive layer adjacent to a substrate, deposition of a doped semiconductor layer adjacent to the substrate, and deposition of an undoped semiconductor layer adjacent to the substrate. A display pixel unit provides reduced capacitative coupling between a pixel electrode and a source line. The unit includes a transistor, the pixel electrode, and the source line. The source line includes an extension that provides a source for the transistor. A patterned conductive portion is disposed adjacent to the source line.

Abstract: A non-linear element is formed on a flexible substrate by securing the substrate to a rigid carrier, forming the non-linear element, and then separating the flexible substrate from the carrier. The process allows flexible substrates to be processed in a conventional fab intended to process rigid substrates. In a second method, a transistor is formed on a insulating substrate by forming gate electrodes, depositing a dielectric layer, a semiconductor layer and a conductive layer, patterning the conductive layer to form source, drain and pixel electrodes, covering the channel region of the resultant transistor with an etch-resistant material and etching using the etch-resistant material and the conductive layer as a mask, the etching extending substantially through the semiconductor layer between adjacent transistors.

Abstract: A non-contacting sensor based on inductive coupling for detecting failure initiation, and crack propagation in composite materials is disclosed. A very low cost crack sensing transducer or test pattern that can be imbedded into a structural material, interrogated, and powered wirelessly is described. A detection method for interrogating the crack sensor utilizing RF inductive coupling is disclosed. The proposed sensor consists of minimal components resulting in maximum reliability.

Abstract: Transistors are formed by depositing at least one layer of semiconductor material on a substrate comprising a polyphenylene polyimide. The substrate permits the use of processing temperatures in excess of 300° C. during the processes used to form the transistors, thus allowing the formation of high quality silicon semiconductor layers. The substrate also has a low coefficient of thermal expansion, which closely matches that of silicon, thus reducing any tendency for a silicon layer to crack or delaminate.

Abstract: A thin-film transistor array comprises at least first and second transistors. Each of the first and second transistors include a shared silicon layer, i.e., an active layer, having a thickness less than approximately 40 nm. The shared silicon layer extends continuously between the first and second transistors. The silicon layer may consist of unpatterned silicon. Heavily doped material may not be required at metal-silicon contact interfaces.