Abstract: A system includes a wearable article and a housing assembly including a receptacle defining a chamber and having an access opening providing access to the chamber to removably receive an electronic module within the chamber. The housing assembly further includes an interface having first and second electrical contacts exposed to the chamber. First and second conductive leads are connected to the electrical contacts through the bottom side of the receptacle to place the leads in electronic communication with the contacts. The housing assembly is bonded between top and bottom layers of material forming a portion of the wearable article, such that the layers are bonded to the receptacle by a bonding material.

Abstract: A thermal bend actuator includes: a thermoelastic beam for connection to drive circuitry; and a passive beam mechanically cooperating with the thermoelastic beam, such that when a current is passed through the thermoelastic beam, the thermoelastic beam expands relative to the passive beam resulting in bending of the actuator. The thermoelastic beam wherein the thermoelastic beam is comprised of an aluminium alloy. The aluminium alloy comprises a first metal which is aluminium, a second metal, and at least 0.1 at. % of a third metal selected from the group consisting of: copper, scandium, tungsten, molybdenum, chromium, titanium, silicon and magnesium.

Abstract: A thermal bend actuator includes: a thermoelastic beam for connection to drive circuitry; and a passive beam mechanically cooperating with the thermoelastic beam, such that when a current is passed through the thermoelastic beam, the thermoelastic beam expands relative to the passive beam resulting in bending of the actuator. The thermoelastic beam wherein the thermoelastic beam is comprised of an aluminium alloy. The aluminium alloy comprises a first metal which is aluminium, a second metal, and at least 0.1 at. % of a third metal selected from the group consisting of: copper, scandium, tungsten, molybdenum, chromium, titanium, silicon and magnesium.

Abstract: An inkjet printhead integrated circuit includes: a substrate having a silicon layer; a nozzle plate disposed on the silicon layer; and embedded inkjet nozzle devices. Each inkjet nozzle device includes a nozzle chamber having a roof actuator; drive circuitry laterally disposed relative to the nozzle chamber; a connection arm extending parallel with the nozzle plate from the actuator towards the drive circuitry; and a metal via interconnecting each connection arm and the drive circuitry, the metal via extending perpendicularly to the nozzle plate. The drive circuitry is positioned proximal the nozzle plate relative to a plane of the floor.

Abstract: An inkjet printhead integrated circuit includes: a substrate having a silicon layer; a nozzle plate disposed on the silicon layer; and embedded inkjet nozzle devices. Each inkjet nozzle device includes a nozzle chamber having a roof actuator; drive circuitry laterally disposed relative to the nozzle chamber; a connection arm extending parallel with the nozzle plate from the actuator towards the drive circuitry; and a metal via interconnecting each connection arm and the drive circuitry, the metal via extending perpendicularly to the nozzle plate. The drive circuitry is positioned proximal the nozzle plate relative to a plane of the floor.

Abstract: An inkjet printhead integrated circuit includes: a silicon-on-insulator substrate having a first layer of silicon, an insulator layer disposed on the first layer of silicon and a second layer of silicon disposed on the insulator layer; a nozzle plate disposed on the second layer of silicon; and embedded inkjet nozzle devices. Each inkjet nozzle device includes a nozzle chamber defined in the second layer of silicon, each nozzle chamber having a roof which is part of the nozzle plate; an actuator for ejecting ink through the nozzle opening; and drive circuitry connected to the actuator.

Abstract: A method used to form a semiconductor device having a capacitor comprises placing a semiconductor wafer assembly into a chamber of a plasma source, the wafer assembly comprising a layer of insulation having at least one contact therein and a surface, and further comprising a conductive layer over the surface and in the contact. Next, in the chamber, a layer of etch resistant material is formed within the contact over the conductive layer, the etch resistant material not forming over the surface.

Abstract: A plasma etch process for etching a dielectric material employing two primary etchants at low flows and pressures, and a relatively low temperature environment within the etch chamber. The two primary etchant gases are CHF3 and CH2F2, delivered at flow rates on the order of between about 10 sccm and 40 sccm for CHF3 and between about 10 sccm and 40 sccm for CH2F2. Small quantities, on the order of 10 sccm or less, of other gases such as C2HF5 and CF4 may be added.

Abstract: Methods and apparatus for etching substrates such as silicon wafers are provided. In one specific approach, a surface of the substrate assembly is covered with a resist that is patterned to define features to be etched. In this approach, the surface is then exposed to a plasma in a plasma etcher so that surface areas not covered with the resist are etched, while the thickness of the resist increases or etches at a rate that is at least ten times slower than that of the exposed areas of the surface. This etching process can be followed with a conventional plasma etch. By combining the etching that increases the resist thickness with the conventional etching of resist in which the resist thins during etching, features having high-aspect-ratios can be etched.

Abstract: A method for grounding a semiconductor substrate pedestal during a portion of a high voltage power bias oscillation cycle to reduce or eliminate the detrimental effects of feature charging during the operation of a plasma reactor.

Abstract: A method of anisotropically etching a semiconductive substrate uses a hydrofluorocarbon etch gas with an etch selectivity fluorocarbon gas. The fluorocarbon gas is used under conditions that enhance selectivity of the etch to an etch stop layer with respect to a bulk dielectric material such as doped or undoped silicon dioxide. In one method, a silicon dioxide dielectric layer is provided upon an etch stop layer, wherein the etch stop layer comprises silicon dioxide that is doped differently from the silicon dioxide dielectric layer. A gaseous etchant including a hydrofluorocarbon etch gas and a fluorocarbon selectivity compound is provided, and the silicon dioxide dielectric layer is exposed to the gaseous etchant.

Abstract: In a copper plating process, a seed layer is uniformly deposited over a surface, including lining a high aspect ratio trench defined by that surface. A mask layer is provided using a process that fails to deposit in the trench. In one exemplary embodiment, the failure is due to the decrease in the isotropic flux of neutrals toward the bottom of the trench. Copper is subsequently electroplated. Because the seed layer is exposed only within the trench, copper deposits only therein. The self-aligned mask prevents plating outside of the trench. A chemical-mechanical planarization step removes the mask and the seed layer extending beyond the trench, leaving a copper structure within the trench. The structure may serve as a conductive line, an interconnect, or a capacitor plate.

Abstract: A modulated bias power etching method for etching a substrate is disclosed. The method alternatively deposits and etches material from a low aspect area of an integrated circuit device to form a static area while etching material from a high aspect area. The modulation pulse period and repetition rate are adjusted to permit deposition at low aspect ratio and very little or no deposition at high aspect ratio during the deposition cycle and to permit etching of the material deposited on the low aspect ratio area and etching of the material in the high aspect ratio area during the etching cycle.

Abstract: A plasma process reactor and method is disclosed that allows for greater control in varying the functional temperature range for enhancing semiconductor processing and reactor cleaning. The temperature is controlled by splitting the process gas flow from a single gas manifold that injects the process gas behind the gas distribution plate into two streams where the first stream goes behind the gas distribution plate and the second stream is injected directly into the chamber. By decreasing the fraction of flow that is injected behind the gas distribution plate, the temperature of the gas distribution plate can be increased. The increasing of the temperature of the gas distribution plate results in higher O2 plasma removal rates of deposited material from the gas distribution plate. Additionally, the higher plasma temperature aids other processes that only operate at elevated temperatures not possible in a fixed temperature reactor.

Abstract: A container for use in a processing chamber to lessen the amount of contaminant particles found within the chamber after processing. The container fits closely within the chamber and includes ports for a gas conduit and a vacuum conduit. The container may be locked to the chamber through a locking mechanism and a recess in the container. The container may be guided into the chamber with a plurality of chamfers. The container may be used in inductively coupled plasma chambers, electron cyclotron resonance chambers, and chambers capable of receiving microwaves.

Abstract: In one aspect, the invention encompasses a semiconductor processing method of forming a material over an uneven surface topology. A substrate having an uneven surface topology is provided. The uneven surface topology comprises a valley between a pair of outwardly projecting features. A layer of material is formed over the uneven surface topology. The layer comprises outwardly projecting portions over the outwardly projecting features of the surface topology and has a gap over the valley. The layer is etched, and the etching forms protective material within the gap while removing an outermost surface of the layer. The etching substantially does not remove the material from the bottom of the gap. In another aspect, the invention encompasses a semiconductor processing method of forming a material over metal-comprising lines. A first insulative material substrate is provided. A pair of spaced metal-comprising lines are formed over the substrate.

Abstract: This invention is a hardware modification which permits greater uniformity of etching to be achieved in a high-density-source plasma reactor (i.e., one which uses a remote source to generate a plasma, and which also uses high-frequency bias power on the wafer chuck). The invention addresses the uniformity problem which arises as the result of nonuniform power coupling between the wafer and the walls of the etch chamber. The solution to greatly mitigate the nonuniformity problem is to increase the impedance between the wafer and the chamber walls. This may be accomplished by placing a cylindrical dielectric wall around the wafer. Quartz is a dielectric material that is ideal for the cylindrical wall if silicon is to be etched selectively with respect to silicon dioxide, as quartz it is virtually inert under such conditions.

Abstract: Plasma etching processes using a plasma containing fluorine as well as bromine and/or iodine are suited for high aspect ratio etching of trenches, contact holes or other apertures in silicon oxide materials. The plasma is produced using at least one fluorine-containing source gas and at least one bromine- or iodine-containing source gas. Bromine/iodine components of the plasma protect the aperture sidewalls from lateral attack by free fluorine, thus advantageously reducing a tendency for bowing of the sidewalls. Ion bombardment suppresses absorption of bromine/iodine components on the etch front, thus facilitating advancement of the etch front without significantly impacting taper.

Abstract: A plasma reactor comprises an electromagnetic energy source coupled to a radiator through first and second variable impedance networks. The plasma reactor includes a chamber having a dielectric window that is proximate to the radiator. A shield is positioned between the radiator and the dielectric window. The shield substantially covers a surface of the radiator near the dielectric window. A portion of the radiator that is not covered by the shield is proximate to a conductive wall of the chamber. Plasma reactor operation includes the following steps. A plasma is ignited in a chamber with substantially capacitive electric energy coupled from the radiator. A variable impedance network is tuned so that the capacitive electric energy coupled into the chamber is diminished. The plasma is then powered with substantially magnetic energy.

Abstract: A container for use in a processing chamber to lessen the amount of contaminant particles found within the chamber after processing. The container fits closely within the chamber and includes ports for a gas conduit and a vacuum conduit. The container may be locked to the chamber through a locking mechanism and a recess in the container. The container may be guided into the chamber with a plurality of chamfers. The container may be used in inductively coupled plasma chambers, electron cyclotron resonance chambers, and chambers capable of receiving microwaves.