Abstract: The present invention provides for saving power in a floating point unit. Bypass logic is coupled to the input of the aligner and the multiplier. An aligner bypass is coupled to the output of the aligner and an output of the bypass logic. A multiplier bypass is coupled to the output of the multiplier and an output of the bypass logic. The aligner bypass and the multiplier bypass transmit the output of the aligner and multiplier, or the bypass logic, as a function of an aligner bypass signal and a multiplier bypass signal, respectively. An adder is coupled to the output of the aligner bypass and the multiplier bypass. Clock disable logic is used to selectively enable and disable at least portions of the aligner, multiplier and bypass logic. This is done based on the operation and on the value of the operands.

Abstract: The present invention provides for saving power in a floating point unit. Bypass logic is coupled to the input of the aligner and the multiplier. An aligner bypass is coupled to the output of the aligner and an output of the bypass logic. A multiplier bypass is coupled to the output of the multiplier and an output of the bypass logic. The aligner bypass and the multiplier bypass transmit the output of the aligner and multiplier, or the bypass logic, as a function of an aligner bypass signal and a multiplier bypass signal, respectively. An adder is coupled to the output of the aligner bypass and the multiplier bypass. Clock disable logic is used to selectively enable and disable at least portions of the aligner, multiplier and bypass logic. This is done based on the operation and on the value of the operands.