Patents by Inventor Kevin Duesman

Kevin Duesman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7646016
    Abstract: A method for automatically measuring the modulation transfer function of an imager is disclosed. A opaque mask is placed over selected columns and rows of the imager during fabrication. In the course of an automated process, photons are uniformly shone over the image sensor. The amount of the input signal that flows from the unmasked pixel cells to the masked pixel cells can then be measured and the modulation transfer function can be determined.
    Type: Grant
    Filed: June 22, 2006
    Date of Patent: January 12, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Kevin Duesman, Jeffrey Bruce, Peter P. Altice, Jr., Moshe Reuven, Donald E. Robinson, Ed Jenkins, Joey Shah
  • Patent number: 7375793
    Abstract: Photolithographic processing apparatus and methods are disclosed. In one embodiment, a method of photolithographically patterning a surface of a substrate includes forming a photoreactive layer on the surface of the substrate, transmitting light through a first patterning portion of a first photolithographic mask to expose a first patterned portion of the photoreactive layer, transmitting light through a second patterning portion of a second photolithographic mask to expose a second patterned portion of the photoreactive layer. In an alternate embodiment, transmitting light through the first patterning portion of the first photolithographic mask is performed simultaneously with transmitting light through the second patterning portion of the second photolithographic mask. In a further embodiment, the light being transmitted through the second patterning portion of a second photolithographic mask has already been transmitted through a first transparent portion of the first photolithographic mask.
    Type: Grant
    Filed: April 1, 2004
    Date of Patent: May 20, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Kevin Duesman, Randal Chance
  • Publication number: 20070145464
    Abstract: A memory structure has a vertically oriented access transistor with an annular gate region. A transistor is fabricated such that the channel of the transistor extends outward with respect to the surface of the substrate. An annular gate is fabricated around the vertical channel such that it partially or completely surrounds the channel. A buried annular bitline may also be implemented. After the vertically oriented transistor is fabricated with the annular gate, a storage device may be fabricated over the transistor to provide a memory cell.
    Type: Application
    Filed: February 21, 2007
    Publication date: June 28, 2007
    Inventors: Thomas Voshell, Lucien Bissey, Kevin Duesman
  • Patent number: 7215361
    Abstract: A method for automatically measuring the modulation transfer function of an imager is disclosed. A opaque mask is placed over selected columns and rows of the imager during fabrication. In the course of an automated process, photons are uniformly shone over the image sensor. The amount of the input signal that flows from the unmasked pixel cells to the masked pixel cells can then be measured and the modulation transfer function can be determined.
    Type: Grant
    Filed: September 17, 2003
    Date of Patent: May 8, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Kevin Duesman, Jeffrey Bruce, Peter P. Altice, Jr., Moshe Reuven, Donald E. Robinson, Ed Jenkins, Joey Shah
  • Publication number: 20060256630
    Abstract: A method and apparatus is provided for reducing the current in a memory device. Peripheral device control signals are translated to the wordline off voltage level, such as a negative wordline voltage. The translated signals prevent the peripheral devices from conducting current in the wordline off mode, even if a wordline-to-digitline short should occur. The control signals may include a column select signal for a column select device and an active pull-up signal for a sense amplifier, among others. Additionally, an equalization circuit having high and low resistance components is provided for the memory device. The equalization circuit limits current, even if a wordline-to-digitline short occurs.
    Type: Application
    Filed: July 19, 2006
    Publication date: November 16, 2006
    Inventors: Scott Derner, Stephen Porter, Scot Graham, Ethan Williford, Kevin Duesman
  • Publication number: 20060244473
    Abstract: An IC module, such as a Multi-Chip Module (MCM), includes multiple IC dice, each having a test mode enable bond pad, such as an output enable pad. A fuse incorporated into the MCM's substrate connects each die's test mode enable bond pad to one of the MCM's no-connection (N/C) pins, and a resistor incorporated into the substrate connects the test mode enable bond pads to one of the MCM's ground pins. By applying a supply voltage to the test mode enable bond pads through the N/C pin, a test mode is initiated in the dice. Once testing is complete, the fuse may be blown, and a ground voltage applied to the test mode enable bond pads through the ground pins so the resistor disables the test mode in the dice and initiates an operational mode. As a result, dice packaged in IC modules may be tested after packaging.
    Type: Application
    Filed: March 27, 2006
    Publication date: November 2, 2006
    Inventors: Warren Farnworth, James Wark, Eric Nelson, Kevin Duesman
  • Publication number: 20060237755
    Abstract: A method for automatically measuring the modulation transfer function of an imager is disclosed. A opaque mask is placed over selected columns and rows of the imager during fabrication. In the course of an automated process, photons are uniformly shone over the image sensor. The amount of the input signal that flows from the unmasked pixel cells to the masked pixel cells can then be measured and the modulation transfer function can be determined.
    Type: Application
    Filed: June 22, 2006
    Publication date: October 26, 2006
    Inventors: Kevin Duesman, Jeffrey Bruce, Peter Altice, Moshe Reuven, Donald Robinson, Ed Jenkins, Joey Shah
  • Publication number: 20060231025
    Abstract: A programmable material consolidation system includes a platen and an object release element on the platen. The object release element includes a lower surface configured to be secured to the platen and readily removed from the platen. An adhesive coating, which may cover at least a portion of the lower surface, may be formed from a material, such as a radiation-curable polymer, that is tacky when in an uncured state and not as tacky when in a substantially cured state. A nonstick coating on the platen may facilitate ready removal of the object release element therefrom. An upper surface of the object release element may include a material to which an object will adhere, but which may be readily removed from the object once fabrication thereof is complete.
    Type: Application
    Filed: June 9, 2006
    Publication date: October 19, 2006
    Inventors: Warren Farnworth, Kevin Duesman
  • Publication number: 20060226578
    Abstract: A programmed material consolidation method includes use of an object release element for facilitate removal of an object from a platen of programmed material consolation equipment while leaving substantially no residue on the platen or a fabricated object, and without requiring substantial post-release modification of the fabricated object. The object release element may be adhesively secured to a non-stick surface of the platen, with a material that adheres to the platen before being cured and that may be removed from the platen upon curing, or by application of a negative pressure through the platen to the object release element. The object release element may be formed from a material or include coating of a material, such as polyethylene, polyethyleneteraphthalate, or polyethylene ethyl ketone, that adheres to a fabricated object, but may be readily released from the fabricated object (e.g., by peeling).
    Type: Application
    Filed: June 9, 2006
    Publication date: October 12, 2006
    Inventors: Warren Farnworth, Kevin Duesman
  • Publication number: 20060118846
    Abstract: A memory structure having a vertically oriented access transistor with an annular gate region and a method for fabricating the structure. More specifically, a transistor is fabricated such that the channel of the transistor extends outward with respect to the surface of the substrate. An annular gate is fabricated around the vertical channel such that it partially or completely surrounds the channel. A buried annular bitline may also be implemented. After the vertically oriented transistor is fabricated with the annular gate, a storage device may be fabricated over the transistor to provide a memory cell.
    Type: Application
    Filed: August 4, 2005
    Publication date: June 8, 2006
    Inventors: Lucien Bissey, Kevin Duesman
  • Publication number: 20060023493
    Abstract: A method and apparatus is provided for reducing the current in a memory device. Peripheral device control signals are translated to the wordline off voltage level, such as a negative wordline voltage. The translated signals prevent the peripheral devices from conducting current in the wordline off mode, even if a wordline-to-digitline short should occur. The control signals may include a column select signal for a column select device and an active pull-up signal for a sense amplifier, among others. Additionally, an equalization circuit having high and low resistance components is provided for the memory device. The equalization circuit limits current, even if a wordline-to-digitline short occurs.
    Type: Application
    Filed: July 29, 2004
    Publication date: February 2, 2006
    Inventors: Scott Derner, Stephen Porter, Scot Graham, Ethan Williford, Kevin Duesman
  • Patent number: 6954385
    Abstract: A sense circuit for reading a resistance level of a programmable conductor random access memory (PCRAM) cell is provided. A voltage potential difference is introduced across a PCRAM cell by activating an access transistor from a raised rowline voltage. Both a digit line and a digit complement reference line are precharged to a first predetermined voltage. The cell being sensed has the precharged voltage discharged through the resistance of the programmable conductor memory element of the PCRAM cell. A comparison is made of the voltage read at the digit line and at the reference conductor. If the voltage at the digit line is greater than the reference voltage, the cell is read as a high resistance value (e.g., logic HIGH); however, if the voltage measured at the digit line is lower than that of the reference voltage, the cell is read as a low resistance value (e.g., logic LOW).
    Type: Grant
    Filed: August 16, 2004
    Date of Patent: October 11, 2005
    Assignee: Micron Technology, Inc.
    Inventors: Stephen L. Casper, Kevin Duesman, Glen Hush
  • Patent number: 6872509
    Abstract: Photolithographic processing apparatus and methods are disclosed. In one embodiment, a method of photolithographically patterning a surface of a substrate includes forming a photoreactive layer on the surface of the substrate, transmitting light through a first patterning portion of a first photolithographic mask to expose a first patterned portion of the photoreactive layer, transmitting light through a second patterning portion of a second photolithographic mask to expose a second patterned portion of the photoreactive layer. In an alternate embodiment, transmitting light through the first patterning portion of the first photolithographic mask is performed simultaneously with transmitting light through the second patterning portion of the second photolithographic mask. In a further embodiment, the light being transmitted through the second patterning portion of a second photolithographic mask has already been transmitted through a first transparent portion of the first photolithographic mask.
    Type: Grant
    Filed: August 5, 2002
    Date of Patent: March 29, 2005
    Assignee: Micron Technology, Inc.
    Inventors: Kevin Duesman, Randal Chance
  • Publication number: 20050058837
    Abstract: An object release element includes a lower surface configured to be secured to a platen of stereolithographic fabrication equipment while an object is being fabricated on an opposite, upper surface thereof and readily removed from the platen following such fabrication. The upper surface may include a material to which an object will adhere, but which may be readily removed from the object once fabrication thereof is complete. An adhesive coating, which may cover at least a portion of the lower surface, may be formed from a material, such as a light-curable polymer, that is tacky when in an uncured state and not tacky when in a substantially cured state. Methods of using the object release element may include at least partially coating a support surface of a platen with a nonstick material to facilitate ready removal of the object release element therefrom following substantial curing of the adhesive coating.
    Type: Application
    Filed: September 16, 2003
    Publication date: March 17, 2005
    Inventors: Warren Farnworth, Kevin Duesman
  • Publication number: 20050056945
    Abstract: A semiconductor wafer or other bulk semiconductor substrate having a plurality of dice thereon is manufactured using conventional processing techniques. The wafer is subjected to testing to identify functional and nonfunctional dice. The locations of the functional dice are analyzed to determine the location of immediately adjacent or closely proximate functional dice. A group of functional dice is identified and an interconnection circuit is formed therebetween. The functional die group, once interconnected, is then segmented from the wafer while maintaining the unitary integrity of the functional die group as well as the associated interconnections between dice. Modules including one or more functional die groups and methods of fabricating functional die groups and modules are also disclosed.
    Type: Application
    Filed: September 16, 2003
    Publication date: March 17, 2005
    Inventors: Aron Lunde, Kevin Duesman, Timothy Cowles
  • Publication number: 20050059175
    Abstract: A semiconductor wafer or other bulk semiconductor substrate having a plurality of dice thereon is manufactured using conventional processing techniques. The wafer is subjected to testing to identify functional and nonfunctional dice. The locations of the functional dice are analyzed to determine the location of immediately adjacent or closely proximate functional dice. A group of functional dice is identified and an interconnection circuit is formed therebetween. The functional die group, once interconnected, is then segmented from the wafer while maintaining the unitary integrity of the functional die group as well as the associated interconnections between dice. Modules including one or more functional die groups and methods of fabricating functional die groups and modules are also disclosed.
    Type: Application
    Filed: August 20, 2004
    Publication date: March 17, 2005
    Inventors: Aron Lunde, Kevin Duesman, Timothy Cowles
  • Publication number: 20050057655
    Abstract: A method for automatically measuring the modulation transfer function of an imager is disclosed. A opaque mask is placed over selected columns and rows of the imager during fabrication. In the course of an automated process, photons are uniformly shone over the image sensor. The amount of the input signal that flows from the unmasked pixel cells to the masked pixel cells can then be measured and the modulation transfer function can be determined.
    Type: Application
    Filed: September 17, 2003
    Publication date: March 17, 2005
    Inventors: Kevin Duesman, Jeffrey Bruce, Peter Altice, Moshe Reuven, Donald Robinson, Ed Jenkins, Joey Shah
  • Publication number: 20050018493
    Abstract: A sense circuit for reading a resistance level of a programmable conductor random access memory (PCRAM) cell is provided. A voltage potential difference is introduced across a PCRAM cell by activating an access transistor from a raised rowline voltage. Both a digit line and a digit complement reference line are precharged to a first predetermined voltage. The cell being sensed has the precharged voltage discharged through the resistance of the programmable conductor memory element of the PCRAM cell. A comparison is made of the voltage read at the digit line and at the reference conductor. If the voltage at the digit line is greater than the reference voltage, the cell is read as a high resistance value (e.g., logic HIGH); however, if the voltage measured at the digit line is lower than that of the reference voltage, the cell is read as a low resistance value (e.g., logic LOW).
    Type: Application
    Filed: August 16, 2004
    Publication date: January 27, 2005
    Inventors: Stephen Casper, Kevin Duesman, Glen Hush
  • Publication number: 20040191702
    Abstract: Photolithographic processing apparatus and methods are disclosed. In one embodiment, a method of photolithographically patterning a surface of a substrate includes forming a photoreactive layer on the surface of the substrate, transmitting light through a first patterning portion of a first photolithographic mask to expose a first patterned portion of the photoreactive layer, transmitting light through a second patterning portion of a second photolithographic mask to expose a second patterned portion of the photoreactive layer. In an alternate embodiment, transmitting light through the first patterning portion of the first photolithographic mask is performed simultaneously with transmitting light through the second patterning portion of the second photolithographic mask. In a further embodiment, the light being transmitted through the second patterning portion of a second photolithographic mask has already been transmitted through a first transparent portion of the first photolithographic mask.
    Type: Application
    Filed: April 1, 2004
    Publication date: September 30, 2004
    Inventors: Kevin Duesman, Randal Chance
  • Patent number: 6791885
    Abstract: A sense circuit for reading a resistance level of a programmable conductor random access memory (PCRAM) cell is provided. A voltage potential difference is introduced across a PCRAM cell by activating an access transistor from a raised rowline voltage. Both a digit line and a digit complement reference line are precharged to a first predetermined voltage. The cell being sensed has the precharged voltage discharged through the resistance of the programmable conductor memory element of the PCRAM cell. A comparison is made of the voltage read at the digit line and at the reference conductor. If the voltage at the digit line is greater than the reference voltage, the cell is read as a high resistance value (e.g., logic HIGH); however, if the voltage measured at the digit line is lower than that of the reference voltage, the cell is read as a low resistance value (e.g., logic LOW).
    Type: Grant
    Filed: February 19, 2002
    Date of Patent: September 14, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Stephen L. Casper, Kevin Duesman, Glen Hush