Abstract: An arrangement which includes a telephone and an interface unit, which interfaces the telephone to both a standard switched telephone communications network and an Internet communications network, is disclosed. The interface unit includes an input coupled to the telephone to receive audio information and two output ports configured to be respectively coupled to the standard switched telephone communications network and the Internet communications network. A processing unit couples the audio information received from the telephone to the first output port when the telephonic communication is to be performed using the standard switched telephone communications network. Alternatively, the processing unit processes the audio information received from the telephone in accordance with standard Internet transfer protocols and couples the processed audio information to the second output port when the telephonic communication is to be performed using the Internet communications network and the standard protocols.

Abstract: An arrangement which includes a telephone and an interface unit, which interfaces the telephone to both a standard switched telephone communications network and an Internet communications network, is disclosed. The interface unit includes an input coupled to the telephone to receive audio information and two output ports configured to be respectively coupled to the standard switched telephone communications network and the Internet communications network. A processing unit couples the audio information received from the telephone to the first output port when the telephonic communication is to be performed using the standard switched telephone communications network. Alternatively, the processing unit processes the audio information received from the telephone in accordance with standard Internet transfer protocols and couples the processed audio information to the second output port when the telephonic communication is to be performed using the Internet communications network and the standard protocols.

Abstract: Serial bus modules with unique multibit identifications that may be searched with multiple modules on a single bus. Modules may contain temperature history per integrated Arrhenius temperature dependent signal. Modules may be packaged as tokens or as two or three lead plastic plastic, also with the three lead packages further functionality as sensors or switches may be incorporated into the modules.

Abstract: A temperature-controlled counter/clock arrangement is provided where th rate or frequency of the counting is temperature dependent. This allows for a measuring of thermal accumulation and/or history. The temperature sensing is based upon the use of the varying current that will flow through a toward biased semiconductor diode. In one embodiment a constant voltage source is used so that the current variation will follow Arrhenius's law.

Abstract: A method of communicating information between a host device and a potentially portable module device which measures thermal accumulation over time via a temperature controlled counter. The temperature controlled counter may operate using substantially Arrhenius' law. The host device communicates with the portable module via a single wire bidirectional data bus. The single wire bus and one-wire communication protocol allows data flow between a host and a plurality of devices connected to the single wire bus. The single wire bus allows for a great versatility of uses for the portable module.

Abstract: A system architecture which provides efficient data communication, over a one-wire bus, with a portable data module which does not necessarily include any accurate time base whatsoever. The time base in the module can be extremely crude (e.g. more than 4:1 uncertainty). An open-collector architecture is used, with electrical relations defined to absolutely minimize the drain on the portable module's battery. The protocol has been specified so that the module never sources current to the data line, but only sinks current. The protocol includes signals for read; write-zero; write-one; and reset. Each one-bit transaction is initiated by a falling edge from the host. The time base in the module defines a delay, after which (in write mode) the module tests the data state of the data line. In read mode, after a falling edge the module does or does not turn on its pull-down transistor, depending on the data value.

Abstract: A communication circuit is provided in which reads from a device are controlled by sensing a transition by a host communicating with a device. The device then accepts a one which holds the line high for a predetermined time period or accepts a zero when the line is held high for a different time period. The sending of data is accomplished in a symmetrical relationship by having the device after the host pulls the line high by either by allowing the line to remain high or forcing the line to ground within the requisite time periods. This allows the "slave" device to consume almost no power in either the read or the write modes.

Abstract: A digital rheostat or potentiometer which provides both increment and decrement operations from a single input such as a pushbutton. A certain pattern of input actuations will cause the direction of change to reverse. Settings of the potentiometer are stored in nonvolatile memory.

Abstract: A serial-port memory is positioned in a substantially token-shaped body. The substantially token-shaped body has a perimeter and a flange extending from a portion of the perimeter. The serial-port memory comprises a serial port, a scratchpad memory coupled to the serial port, a second memory coupled to the scratchpad memory; and control logic coupled to the serial port and the scratchpad and second memories. The control logic transfers information from the scratchpad memory to the second memory as a block pursuant to a block transfer command received at the serial port.

Abstract: An electronic token has at least two conductive surfaces which form either in total or in part a crush resistant casing in which a semiconductor memory is placed. Coupled to the two conductive surfaces is a set of input logic which is used to detect whether or not the first conductive surface is coupled to a device in which a first voltage or a second voltage is present and in which data can be stored in the semiconductor memory accordingly. Output logic is also provided so as to selectively poll the first conductive surface of said casing towards the second voltage with the output logic being electronically coupled to the semiconductor memory so that data may be retrieved from the stored memory. The stored information may be used for controlling access to items, for example as a lock. It may further be used as an inventory control device, postage control device, currency device for the sale of goods.

Abstract: A nonvolatile memory, includes multiple nonvolatile registers with each nonvolatile register including memory cells, and further includes circuitry that writes information to each of the nonvolatile registers one at a time, in a rotating order to prolong the prevention of tunneling oxide breakdown.

Abstract: A communication module comprises a substantially token-shaped body with first and second electrically conductive surface areas. The first and second surface areas are electrically isolated from each other and circuitry is positioned in the cavity within the substantially token-shaped body, and has connections to said first and second areas. The substantially token-shaped body has a perimeter around it. The first and second electrically conductive surface areas form a substantial portion of the substantially token-shaped body. The first and second electrically conductive surface areas form a cavity. One of the surface areas forming a flange around the perimeter of the substantially token-shaped body. The flange preferably resides in one geometric plane. The circuitry provides for the receipt and transmission of digital signals that are determined as voltage differences between said first and second areas.

Abstract: A digital rheostat or potentiometer which provides both increment and decrement operations from a single input such as a pushbutton. A certain pattern of input actuations will cause the direction of change to reverse. Settings of the potentiometer are stored in nonvolatile memory.

Abstract: A printer port adapter which permits electronic keys to be accessed through the printer port of the PC, without disrupting the normal operation of the printer port in any mode of operation whatsoever. The electronic keys used have a one-wire signal interface, and this interface can be inserted into the full standard ISA printer port pin assignment, as well as the all known nonstandard additional assignments which have been overlaid onto the standard printer port.

Abstract: An integrated circuit which includes not only a real time clock, but also an elapsed time counter, and a third counter. The elapsed time counter measures the total number of seconds during which a system has been powered up. The third counter is a "cycle counter," which measures the number of times a power cycle (power-up and power-down) has occurred. Thus, by reading the cycle counter and the elapsed time indicator, the general power history of a system can readily be determined, even if the system itself has totally failed. This integrated circuit is battery backed, and is advantageously combined with a system for which power history must be maintained.

Abstract: A low-power timekeeping integrated circuit, using a double-buffered memory architecture: The user can freely read from user memory at any time, and an internal clock periodically updates a set of timekeeping registers. Transfer from the timekeeping registers to user memory (for update of the data) is performed as a block transfer, asynchronously and invisibly to the user. A special timing-window requirement is used to avoid access collision problems: each edge of the one-hertz oscillator signal is delayed slightly, and it is the delayed signal which actually clocks the update to the timekeeping registers. After a further small delay (long enough to allow for worst-case ripple-through delays in the timekeeping registers), a latched signal (NO.sub.-- RIPPLE, in the presently preferred embodiment) is driven active. The signal NO.sub.-- RIPPLE shows that any rippling has been completed and that access is safe. Thus, transfer will occur or not, but will never be cut short.

Abstract: A battery-backed ancillary power-management chip, in combination with a battery-backed microprocessor or microcontroller, permits a low-power system to achieve a zero-power standby mode with full nonvolatility. The ancillary chip contains transmission gates which can cut off the connection between two other chips if one of them is turned off. This avoids problems of power leakage, substrate pumping, etc., when two chips which are connected together can be independently powered up or powered down.Also provided is a portable data module, which includes a microprocessor and a large LCD display. The disclosed inventions permit the user to operate the display without powering up the microprocessor (to preserve a complex display, e.g. when the user has provided no inputs for a certain length of time), or to operate the microprocessor without the display (e.g. for data transfer or reduction operations).

Abstract: An integrated circuit with power-up-warning circuitry wherein time integration and voltage level testing are done sequentially instead of simultaneously. A reference voltage is generated by current sourced to a reference voltage circuit, and this reference voltage is used as follows: An inverter receives the reference voltage as an input, and switches when the power supply becomes high enough that the reference voltage appears as a "low" level. When this inverter switches, current begins to be sourced to a timing capacitor. After the timing capacitor has charged up to a predetermined level, the current source to the reference-voltage node is turned off, and the power-up-warning signal (which has been driven high by output buffers) is turned off.

Abstract: An integrated circuit which provides multiple independently accessible low-on-state-resistance switches, using conventional CMOS technology. Charge pumping is used to boost the gate voltage to lower the on-state resistance. The surface of the chip consists primarily of a few very large path transistors. This chip is perferably combined with a power management chip which provides logic outputs, and the large PMOS switches are used for controlling the power supply to various other chips, such as SRAMs.

Abstract: A test system in a standalone chassis without a power cord. The testing subsystem (e.g. a spectrophotometer) is microprocessor-controlled, and the microprocessor is disconnected from the battery during normal operation. An ancillary integrated circuit controls the power supply to the microprocessor, and periodically powers up a proximity sensor subsystem (e.g. a photodiode/LED pair), without powering up the microprocessor. The ancillary circuit powers up the microprocessor IF the proximity sensor subsystem, after being activated, indicates that a sample has been inserted by a user. The microprocessor can then operate the testing subsystem, and provide output data to a display driver accordingly.