Abstract: A system and method for slave-side arbitration includes a plurality of master devices, a target device, and an arbitrator for arbitrating access to the target device by the master devices. Queuing devices, such as FIFO buffers, are respectively associated with master devices and communicate information regarding retained target device access requests to the arbitrator. The information may be communicated to the arbitrator by sending it to the arbitrator, or may be provided as status information that is accessed by the arbitrator. The arbitrator uses an arbitration scheme and information regarding retained transaction requests to determine which master device should be granted access to the target device. The arbitration system and method can be used in an integrated circuit with multiple embedded processors, and can be implemented in a document processing system to improve overall system performance over conventional slave-side arbitration schemes.

Abstract: A serial load controller and method for loading at least one input data bit serially into a memory. The memory is interfaced to a data bus and an address bus. The serial load controller includes a counter generating an internal address pointer signal in response to a first control signal. The first control signal indicates that the input data bit is to be transferred serially into the memory. The counter is responsive to the first control signal to reset the internal address pointer to an initial value. A multiplexer is coupled to select one of the address bus and the internal address pointer signal as an output address bus in response to the first control signal. Suitable transceivers or other bus drivers are provided for driving at least a first input data bit onto the data bus in response to the clock pulse.

Abstract: A method for controlling a high speed memory unit M to be read from, and written to, as initiated by clock signals of comparable speed, this method involving: providing a timing coordinator unit with bi-stable store for storing and presenting certain input signals to the memory unit in conjunction with the clock signals so as to be immediately useable thereby and so that the memory unit can responsively output data to a user stage; these input signals being arranged to include commands R/W to Read or Write, Address signals and Data signals; and the memory unit being maintained in “ready-to-read” condition at all times except during receipt of write commands.

Abstract: The invention includes apparatus for controlling a high speed memory unit M that is written to on every cycle and read from on every cycle except during receipt of write commands. The apparatus includes a timing coordinator with bi-stable storage means that store and present certain signals to the memory in conjunction with clock signals so as to be immediately usable by the memory, and so that the memory can responsively output data to a user. The signals include commands R/W to Read or Write, Address signals and Data signals.

Abstract: An apparatus for and method of granting access to a shared resource wherein the shared resource is accessed by a plurality of users. In a first exemplary embodiment of the present invention, a priority controller can assign priority to a number of users based upon the combination of shared resource request signals received by the priority controller. For each combination of shared resource request signals, a different priority may be assigned to each user by the priority controller. In another exemplary embodiment of the present invention, each user may supply additional information bits to the priority controller to indicate a "requested priority" for a the shared resource. The priority controller then weighs the priority requests from each user, including the additional information bits, and determines an optimum priority assignment. That is, the users themselves may influence the priority assigned thereto by providing the additional information bits to the priority controller.

Abstract: An apparatus for and method of providing a system whereby a number of processors may communicate with a memory device and wherein the memory device may operate at a slower speed without substantially reducing the band pass of the computer system. Further, one or more of the processors may have a different data word width from the other processors and from the memory device. The present invention may minimize the amount of wasted memory bits contained therein by concatenating data words such that the resulting data word substantially matches the word width of the memory device. The present invention further allows predefined portions of a data word to be placed in an order and concatenated with predefined portions of the same data word or with predefined portions of other data words. A number of predetermined formats define the selection and the order that the predefined portions may be placed. Various formats are contemplated and are described herein.

Abstract: An image processing hardware element that may be used to implement any number of data manipulation methods. The hardware element may be dedicated to the selected manipulation method such that maximum performance may be attained. The hardware element may be programmed to implement a particular manipulation method by simply down loading new values into the hardware element.