Abstract: A method and system for monitoring the performance of a instruction pipeline is provided. The processor may contain a performance monitor for monitoring for the occurrence of an event within a data processing system. An event to be monitored may be specified through software control, and the occurrence of the specified event is monitored during the execution of an instruction in the execution pipeline of the processor. A particular instruction may be specified to execute within a threshold time for each stage of the instruction pipeline. The specified event may be the completion of a single tagged instruction beyond the specified threshold interval for a stage of the instruction pipeline.

Abstract: A method and system for debugging the execution of an instruction within an instruction pipeline is provided. A processor in a data processing system contains instruction pipeline units. An instruction may be tagged, and in response to an instruction pipeline unit completing its processing of the tagged instruction, a stage completion signal is asserted. An execution monitor external to the pipelined processor monitors the stage completion signals during the execution of the tagged instruction. The execution monitor may be a logic analyzer that displays the stage completion signals in real-time on a display device of the execution monitor. An instruction to be tagged may be selected based upon an instruction selection rule, such as the address of the instruction.

Abstract: The present invention is embodied in a clock controller for generating and controlling the phase alignment of a plurality of ratioed sub-clocks. A master clock is preferably input to a clock splitter to provide a plurality of slave clocks. Phase holds, generated from the slave clocks, are then used to gate each of the slave clocks to produce ratioed clocks that produce phase aligned clock pulses at integer factors of the master clock frequency. The clock controller controls the ratioed clocks by processing commands to start, stop, or pulse the ratioed clocks.

Abstract: A system and method for allowing different operating systems to be utilized in a multiprocessing system is provided in which each of the different operating systems requires different types of interrupt controllers. The system and method comprises detecting which of the at least two different types of operating systems is utilized within the multiprocessing system, and then selecting the appropriate interrupt controller from the different types of interrupt controllers.